Getting the PCB Ready for Manufacturing
We continue our work so for your convenience here the project files you should have so far: first_project_pcb2.zip (8.5 KB)
We have not really looked at the requirements for manufacturing this board until now. For example, we used the KiCad default rules instead of defining them based on our manufacturers capabilities. Nor did we define our own electrical requirements.
In a typical project you will start with first defining these rules. We show this here at the end as it is a more advanced topic that requires all the knowledge you got so far.
What Influences the Design Rules?
There are two major influences to your design rules. The manufacturers capabilities define absolute limits and your own design requirements can define other limits (not violating the absolute limits).
Where do I get the Rules for my Manufacturer?
Every manufacturer has a set of rules that depend on their manufacturing capabilities. These rules map their manufacturing tolerances to board feature sizes and clearances. Typically, such definitions are found on the manufacturers website. If they are not found there then you might need to ask for them by mail.
Be aware that the design rules can differ greatly between different manufacturers and also between different options of the same manufacturer. (For example the copper layer thickness can influence the minimum soldermask to copper clearance for pads.)
A manufacturers spec sheet could look similar to the table below. (Reduced spec sheet showing only the things we care about for this tutorial. I do not name the manufacturer here as i do not want to show any bias.)
Specification |
<20µm Cu |
21 … 35µm Cu |
36 … 45µm Cu |
Clearance Pad to Pad |
50µm |
75µm |
90µm |
Clearance Track to Pad |
50µm |
75µm |
90µm |
Clearance Track to Track |
50µm |
75µm |
90µm |
Minimum Track Width |
50µm |
75µm |
90µm |
Minimum Mask Land Width |
45µm |
45µm |
60µm |
Minimum Mask cutout to trace |
50µm |
50µm |
50µm |
Minimum Mask clearance |
50µm |
50µm |
50µm |
Clearance Drill to Copper |
0.2mm |
0.2mm |
0.2mm |
Minimum copper restring |
250µm/100µm |
250µm/100µm |
250µm/100µm |
Minimum Drill |
0.2mm |
0.2mm |
0.2mm |
The particular manufacturer I looked at had a contradiction for the copper restring within their ruleset. I needed to contact them to get clarification about that. Be prepared that this can also happen with your manufacturer (The reasoning behind the contradiction was that they have two different drill processes with differing tolerances. I could have selected the option with the tighter tolerances which would have resulted in a smaller restring but it would have cost a bit more and the delivery time would have increased.)
Other Sources for Design Rules
In addition to manufacturing constrains you can also have electrical constrains. One such example is defining a trace width larger than the manufactuers suggestion for high current traces to limit voltage drop. The inbuild track width calculators (found in the PCB calculator tool of the main window) can be used to determine these requirements. Or you can use an online tool of your choice.
Another parameter can be a larger copper to copper clearance required for high voltage designs. Here you will most likely need to follow an industry standard or government regulations.
We will require the GND and V+ net to have a minimum width of 0.4mm and a clearance of 0.2mm for the purpose of this tutorial (No real reason, just to show how it is done)
Design Rules in KiCad
Until now, we used the default settings for the design rules. KiCad currently has a bare minimum DRC system. This makes it easy to define the rules but limits what can be done. (Future versions will be more powerful and therefore also more complex.)
From Pcbnew start the board setup dialog found in the file menu (File->Board setup). This dialog is split between a tree view of the possible settings pages to the left and the settings input view. Of note in this tool is that every entry in the tree view defines settings (Even the top layer!)
Settings Page “Design Rules”
This page defines the absolute limits for PCB features which includes the minimum track width as well as minimum sizes for vias and their drills. The same page is also responsible for enabling advanced (more expensive to produce) vias.
We need to map the given manufactuer values to the respective settings here:
- minimum track with is given directly as 75µm=0.075mm
- minimum via drill from the minimum drill size 0.2mm
- minimum via diameter from the drill size and required restring: 0.2+2*0.25 = 0.7mm
Settings Page “Solder Paste/Mask”
This page defines the clearances between copper pads and the mask or paste layer. Both of these settings can be overwritten within the footprint or pad settings.
We can encode only the soldermask clearance and soldermask minimum width setting given by the manufacturer. The distance between mask and trace can not be encoded here, it needs to be respected within the net clearances.
The paste clearances will depend on the stencil manufacturer. We leave them at the default values for this tutorial.
Settings Page “Net Classes”
We first setup the default net class to the manufacturer minimum requirements. We set the track width to 0.075mm and the clearance to 0.1mm. We could set the clearance to 0.75mm but then we do violate the mask to trace requirement given by the manufacturer. (We can sadly not give a separate definition between mask cutout and trace)
The via sizes are setup to the minimum (0.2mm drill, 0.7mm size)
We use the plus button to add a new net class. Name it “Supply” and set it up with 0.4mm trace width and 0.2mm clearance (as we imagined we would require for our system)
We also need to assign this net class to our supply nets. For that select the Supply net class in the assign net class drop down menu. Then select the GND and V+ nets in the net lists and use the assign to selected nets button to get the nets into the supply net class.
Updating the pcb with the new limits
Make sure you set the values as shown previously and use the OK button to save the board settings.
We now need to update the board (again) as we changed the trace widths and clearances of all nets. (This is why one normally does this up front.)
Use block select to select everything. Then right click -> select -> filter selection and activate only vias and tracks.
After that only tracks and vias are selected. Trigger the properties dialog (hotkey “e” or from the right click context menu) which allows manipulating all selected traces and vias at the same time. Select “by netclass” for both the track width and via sizes and press OK.
We now also run DRC to check if everything is ok. I got an error for the V+ trace being too close to pad 1. You might get a different result depending on how exactly you layed out the traces in the last section.
I fix that by dragging the affected track segment away from the pad. What you need to do will possibly differ but will also most likely mean you need to move around traces.
Notice that 0.075mm traces are very thin. We would have enough space to keep them larger. It is suggested that one does not go to the absolute minimum sizes required by the manufacturer unless it is necessary. You can change the netclass again if you want to have additional practice. Otherwise, just leave it as is.
Generating Gerber Files
The final step left is to generate gerber files and sent them to your manufacturer. Some manufacturers provide a web upload for gerber files while others require you to send a mail.
In KiCad gerber output is found via the plot entry in the file menu or via the button in the top toolbar.
In the layers list select the layers you want to have included. In our case the default selection is ok. If you do not plan to have a solder paste stencil manufactured then you can deselect the paste layers.
All other settings highly depend on your manufacturer and your personal preferences. For this tutorial we leave everything as default.
The only thing we do is select a different output directory. Click the folder button to open a file browser like tool and create a folder “gerber” within your project directory. The tool will ask if you want this path to be relative which we suggest you accept. Clicking plot will generate the gerbers as specified.
We now only need to generate the drill files. Click the generate drill files button. All of these settings again depend on your manufacturers requirement, so we can not really give you a step by step explanation. For this tutorial we again keep everything as default and click the generate drill file button.
Likely Gerber Parameter Changes for your Manufacturer
The main parameters which differ between manufactuers are:
- Some manufactuers require the so called protel file naming scheme
- Some manufacturers require the plated and non plated drill definition files to be combined
- Zero formats can be different and selecting the wrong one might explain error messages
- Some manufacturers suggest one sets the soldermask clearance to 0. This allows them to freely select the clearance best fitting the process used for your board. (It gives them more freedoms to pick and choose what process to use. Allows for cheaper production especially in low volume manufacturing at the cost of reduced predictability for you the customer.)