so I opened an existing project, dumped an STM32F105RBTx on it and it has a footprint of:
So why does this not fit with your default rules?
Ah, I see now.
I put it on the PCB, looked at a pad and is shows a pad width of 0.3mm, which leaves 0.2mm for clearance.
The STM32F103C8T6 (It a bit smaller: TQFP-48_7x7mm_Pitch0.5mm) I have on that PCB has a pad width of 0.25 but also has rectangular pads. It’s also an older footprint. It’s a design I started some years ago. It may have been in KiCad V4, but I ported all used schematic symbols and footprints into libraries specific for that project.
So you can use fatter tracks for your “uC” net class. the limiting factor are the wide pads.
Alternatively, you can modify the footprint to use somewhat narrower pads, and then use the same Default Netclass as for the rest of the PCB. In the end it’s just some simple math and addition of numbers. I do remember about a bug that made the PCB fail DRC testing if rotated footprints were used in combination with a netclass that should fit perfectly such as 250um / 250um, and to remedy that a tolerance of 1nm was added and that was deemed adequate.