Hi all,
I’ve been using KiCad since years and I love it.I’m doing a design where the traces width/clearance of a microcontroller must be diferent from the global settings but I’m unable to do it (unless I define a netclass for each signal from/to this IC but it’s not what I want).I attach a snap of the uC footprint for reference.Any help/tip would be much appreciated.Thanks in advance.
P.S.
I’m using version 5.1.9
I’m guessing size here, but I assume your STM32F105RBT6 has a pitch of 0.5mm, and you want to use design rules for the rest of the PCB which the "Track_Width + Clearance** is larger then 0.5mm.
Can you give me some numbers for width and clearance you want to use?
Have you checked the actual capabilities of the fab that will manufacture your PCB’s?
I am not aware of a clean solution for this.
The obvious solution is to use net-ties close to all uC pins in the schematic to separate the uC connection from the rest of the nets, but it’s an ugly solution.
The easiest solution is to ignore your own wishes and change the net class settings to something that fits to your footprint. A similar Footprint I have, has 0.25mm wide pads and that leaves a clearance of also 0.25mm. 0.5mm pitch is not extreme and many PCB manufacturers have no problem whatsoever with this.
So what is your thought process for wanting to do this at all? Maybe you made some false assumptions there.
Maybe this can be done with the rules based DRC which is coming in KiCad-nigthly V5.99.
Yes, there is no easy way to do this in 5.1 but in 5.99 with the new design rule system it is possible.
You just define a rule that applies a tighter clearance and width inside a certain area. There are two ways you might want to define the area in this example. The easiest is to use the insideCourtyard('U3') condition, which will just use the footprint’s courtyard as the rule area. The more flexible option is to draw a rule area and give it a name, then use insideArea('areaName') as the condition. This allows you to apply the rule to a larger or smaller area than the U3 courtyard if that’s what you need.
That said, I agree with paulvdh that an 0.5mm TQFP is not that constrained in terms of trace/space, so I’d be tempted to just make the global board design rules smaller. All of the fabs I use are happy with 0.15mm trace/space with no extra charge.
so I opened an existing project, dumped an STM32F105RBTx on it and it has a footprint of:
Package_QFP:LQFP-64_10x10mm_P0.5mm
So why does this not fit with your default rules?
Ah, I see now.
I put it on the PCB, looked at a pad and is shows a pad width of 0.3mm, which leaves 0.2mm for clearance.
The STM32F103C8T6 (It a bit smaller: TQFP-48_7x7mm_Pitch0.5mm) I have on that PCB has a pad width of 0.25 but also has rectangular pads. It’s also an older footprint. It’s a design I started some years ago. It may have been in KiCad V4, but I ported all used schematic symbols and footprints into libraries specific for that project.
So you can use fatter tracks for your “uC” net class. the limiting factor are the wide pads.
Alternatively, you can modify the footprint to use somewhat narrower pads, and then use the same Default Netclass as for the rest of the PCB. In the end it’s just some simple math and addition of numbers. I do remember about a bug that made the PCB fail DRC testing if rotated footprints were used in combination with a netclass that should fit perfectly such as 250um / 250um, and to remedy that a tolerance of 1nm was added and that was deemed adequate.
Thanks for reply.
Well, the ‘uC’ netclass I define does not actually work bcause the DRC report violations of the clearance on all pins although it’s set to 0.15mm which is actually the pitch of the footprint.I also tried to do a an automatic routing (with FreeRouting) and program seems to go crazy being unable to route tracks from the uC.Also, it put tracks of 0.75mm of width on the power pads of the uC (which are ony 0.3mm) using the deafult netclass and not the specific one.How can I fix this?
What is your experience level with KiCad?
I suspect you are lacking some basic knowledge of how net classes work.
You have made some extra net classes (Kudo’s for that) but have you assigned nets to those net classes?
The screenshot of your Board Setup does have a “Power” net class with a track width of 0.75mm. So it is not using the “Default” net class, which is set to 0.25mm.
What is your experience level with KiCad?
I suspect you are lacking some basic knowledge of how net classes work.
You have made some extra net classes (Kudo’s for that) but have you assigned nets to those net classes?
I use KiCad since many years, I would say I’m more than in an intermediate level.
Yes, I did not assign nets to the ‘uC’ netclasse because if I do it this will affect also the same nets on the rest of the board.
The screenshot of your Board Setup does have a “Power” net class with a track width of 0.75mm. So it is not using the “Default” net class, which is set to 0.25mm.
Sorry I meant the Power netclass and not the default one.The uC footprint can’t have power tracks of 0.75m because pads are only 0.3mm so this misleads the autorouting.I want to use specific tracks/clearance settings for the uC only but without adding all the nets to a netclass affecting the rest of board.
Ok, so there were some typo’s which caused confusion.
But there is still something smelly in:
0.15mm pitch for a footprint would be very small. The TQFP I looked at (ans presumably the same you use) has a pin pitch of 0.5mm and 0.3mm wide pads, which leaves a clearance of 0.2mm. I never like to live on the edge in KiCad, and prefer to leave some decent tolerance for DRC to work with.
Sorry, a typo from me.I meant the pitch of the footprint is 0.5mm but since the ‘uC’ netclass is not recognized the DRC reports errors on all its pins because it refers to clearance of the default netclass which is 0.25mm.I can set the default clearance to 0.15mm but it’s not a good workaround IMHO.Also, the power tracks to the uC cannot be 0.75mm of width, I can lower the defaut value to 0.2-0.25mm but then all power traces on the board will be of these dimensions.
As said before. For the current situation in KiCad V5 you have to split nets with net-ties if you want to use different design rules for a single net.
Also: re-read your posts before posting. You’re making so many typo’s that it becomes hard to apply meaning to what you’re writing and it causes a lot of confusion.
How to properly use net-ties?
Yes, sorry, I’m posting from a mobile, it’s hard to not do any mistakes.
Net-ties are regular schematic symbols and footprints, and therefore used as any other schematic symbols and footprints.
They are also a quick hack and not really well thought out method of solving the problem of having a single net with different net class settings. For example a big fat track to a current sense resistor, and a sense line back for measurement.
The footprints for these are just two SMT pads connected with some copper.
You can use the examples provided in the libraries as a start point to make your custom sized net-ties. Making schematic symbols and footprints in KiCad is quite easy, and for beginners, loading an existing part and modifying is an easy way to start with this part of KiCad.
Also: I really do not care if you’re sending posts from your phone or hanging upside down from the ceiling but I do appreciate if you’re spend a bit more effort in writing your questions carefully.
You should really try to hang upside from they ceiling, the blood will flow all in your brain that will perhaps work better!
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