Can someone please point me in the direction of a complete step by step for getting nets and labels to work in the scope of getting it all translated to PCBnew?
Right now I have a private project that I can’t upload so I will be as descriptive as possible on what I have tried.
I have gone from step A to Z on 3 different tutorials, one official, one on you tube and one I found on Hackaday. All three of them get me to the same point. I either have “tracks too close to pads” errors for every pad or I have rats lines going to every pad but the right one.
I have managed to create the PCB I needed using WireIT and PCBNew alone.
As an experiment I saved the changes and dumped them to a file using WireIt and imported back into Eeschema, nothing changes on the schematic what so ever. Going back to PCBnew results in correct ratslines. I have gone crazy comparing the Nets created by WireIt and Eeschema and can’t see a difference yet one works and the other just frustrates the heck out of me.
My next project is going to be mostly public so I can upload that here or link it from my cloud(lack of privileges here) and I am hoping someone can help me get the correct workflow down in the complete KiCad ecosphere.
You imported what into Eeschema? How did you do it?
I assume that first making a schematic, and then using [F8] to get the netlist into Pbnew works. and that the WireIt plugin (I assume https://github.com/xesscorp/WireIt ) also works by itself.
As far as I know there is no way to back import netlist connections from Pcbnew to Eeschema. I thnk that WireIt is supposed to be used for projects without a schematic at all, or you have to keep the part you do with Eeschema separated from the part with WireIt.
Maybe the SKiDL project is interesting to you. It is a Python library to generate a netlist from within python.
If this does not work, the only workaround I know would be to manually add labels in Eeschema and sync with Pcbnew until the DRC errors are gone.
If you want to keep your private project private, then that’s OK of course, but creating a simple dummy project to make some point clear can be useful.
Indeed, you can show the workflow with even just one resistor: connect the two pins with a wire and give it a net label. Then Update PCB from Schematic (from the Tools menu). Then add another resistor and change the wires in eeschema and update again and see how the ratsnest lines are changed in the layout. If you create a screencast we can see step by step what you are doing even without any explanation.
Thank you for the suggestion, I still can’t upload attachments though.
What I did was record my workflow then go over it. When working with standard libraries and footprints I get working nets. When I create my own I don’t.
I’m pretty sure my faults lie around the point of footprint and symbol label creation. Both on the pins and the Reference labels.
My symbols and Eeschema pass the ERC except for the single “power pin not driven” error.
My Pcbnew DRC looks like this though
Error: REF1 pad 29 not found in NodeMCU:LolinV3.
Error: REF1 pad 27 not found in NodeMCU:LolinV3.
Error: REF1 pad 28 not found in NodeMCU:LolinV3.
Error: REF1 pad 30 not found in NodeMCU:LolinV3.
Error: U2 pad 9 not found in NodeMCU:4ChRelay.
Error: U2 pad 6 not found in NodeMCU:4ChRelay.
…
Furthermore I have pins on components that for some reason get connected to each other within the component themselves and not to the correct nets.
I went over my workflow once more and found that I was placing pads nilly willy without looking at the numbers on some of them. On some of the components that I made in the middle of the night the pads were merely labeled wrong (auto incremented numbers).
Thank you for the support to keep chugging along everyone.