Reverse engineering KiCad project from Gerber files

  • 2022-01-17

The goal of this reverse-engineering tutorial is to re-create a complete KiCad project from partial information assuming the only information available is a schematic in some readable, (but not EDA form, such as a .pdf or a .png picture), and a set of gerber files.
The Gerber files will create a PCB with much PCB information missing, however, using this method is easier than re-designing a PCB from scratch, and can also be extended to any other program that creates Gerber files.
What is “rescued” from Gerber files:

  • PCB outline & mounting holes.
  • All the tracks.
  • Footprint placement (Implicitly encoded in the ends of tracks).
  • Netlist (Implicitly encoded in the location of the tracks).

The steps are:
Create a KiCad project.
Enter the schematic.
Create a PCB using KiCad’s Gerbview.
Cleanup the PCB in Pcbnew.
Assign footprints in the schematic, or with the Footprint Assignment tool.
Eeschema / Tools / Update PCB from Schematic [F8]
Place new footprints over the back-imported copper tracks.
Use DRC to resolve differences and fix mistakes.

Create a KiCad project

For this tutorial, the Project name used is “Gerber_Reverse”

Enter the Schematic

If only a printed version of the schematic is available, that schematic needs to be manually entered into KiCad. The information is useful and it is a simple data entry.
If a schematic in .pdf format is available (or if it can be converted to a .pdf format) then it may be possible to extract more information in a semi-automated way.
Eg: uConfig is one of the many side projects around KiCad. It’s original goal is to extract data from datasheets and create KiCad schematic symbols. A very similar process to recreating schematic symbols from a schematic in .pdf format.
Other similar methods may exist (there are many side projects around KiCad).

For this tutorial, the schematic used was included in the example project used.

Create a PCB using KiCad’s Gerbview

  1. Exit KiCad after naming the project and completing schematic
  2. Create a subdirectory “gerbers” in the newly created project.
  3. Copy all the gerber files into that subdirectory.
  4. Restart the KiCad project manager.
  5. Start Gerbview from KiCad.
  6. Load all the Gerber files: Gerbview / File / Open Gerber Plot File(s)
    The layer section needs to be loaded correctly. A typical set of Gerber files has PCB outline, copper, Solder mask, Silkscreen and possibly more.
  7. Gerbview / File / Export to Pcbnew (KiCad V5)
    Gerbview / File / Export to Pcb Editor (KiCad V6.0.0)

For the board file Name, use the same name as the created KiCad project: “Gerber_Reverse”.
If the newly created project already has a PCB file, overwrite it.

The most important layers are the copper layer(s) and the PCB outline. Layers such as Silkscreen and Solder mask can be useful as a reference. For example, if it is ambiguous which copper layer is the top or the bottom, this can be deduced from the silkscreen… the silkscreen layer for the bottom layer is shown mirrored in gerber files because it’s also viewed from the top and you’re looking “through the PCB”.

For this tutorial 4 layers are exported:

The two copper layers, PCB outline, and the Silkscreen layer. The Silkscreen to “Eco1.User” as a reference will become clear later.

On completion of these steps, Gerbview should now be closed.

Cleanup the PCB in Pcbnew.

Open the created PCB in Pcbnew.
Color for “Eco1.User”, the silkscreen, unfortunately disguises “B.Cu”; that layer having the same color. The problem is remedied with a color change to “Eco1.User” by a double click to the color select in the Layers menu.

The result now clearly shows all the information from the imported layers.

Many obvious faults still exist.

  • No Footprints.
  • Pads have been replaced with via’s.
  • Drills holes are all the same diameter (hole sizes not imported).
  • No real information about zones, only “painted copper”.
  • No texts (on the exported silkscreen) just graphic lines in the form of text.

Cleanup or remove non required information.
The PCB is relatively clean, because it was created with KiCad originally. Other Gerber file sets may create many small tracks, SMT pads and zones that are “painted” (That is, made from lots of small copper segments).

The PCB has a big polygon on F.CU:

This polygon may have some useful information, so is therefore temporarily moved to “Eco2.User” layer (Select the polygon, press e for edit. Change layer to Eco2.User). Hide the Eco2.User layer by removing the checkmark in the Layers Manager.

The edges of the real copper zones have been transformed to many small copper segments. This is useless information so can all be removed. To remove, good use can be made of the “Box Selection” in Kicad. Dragging a box from left to right only selects items that are fully enclosed by the box. (This is useful for lots of small segments). Dragging a box from right to left selects everything in the box plus all items crossing the box boundaries. (This was useful for a reverse-engineered PCB that came from an old version of Protel. In that Gerber file set all copper zones were painted, and consisted of many long horizontal lines).
This cleanup can be tedious, although not difficult, and can be completed relatively quickly with one hand on the mouse, and the other on the [Del] key.


  • All painted copper. (both remnants from zones, painted SMT pads and more).
  • The via’s that have been created from the THT pads.


  • Copper tracks.
  • PCB outline information.
  • Mounting hole information.
  • Real via’s.

Pay Special attention to:

  • Preserving track ends that end in pads. Track ends should end in the center of pads (both for THT and SMT), although this is not always the case in the original design. Note: not all track ends need preserving, however, at least one, for exact locating of footprints (described later) is required.

The following example shows the three THT LED cleanup in the South East corner of the PCB:

(After turning Eco1.User off again, to preserve that information for reference later)
Creating a box by dragging from left to right:

results in this selection:

And a [Del] then shows:

This cleans up 3 footprints with a single delete. Unfortunately, a little too much was deleted. The original footprints were in line but the resulting track ends are not. A [Ctrl + Z] and showing via’s in outline mode demonstrates why: the middle LED had a small track segment from the center of the track. (Highlighted in the screenshot).

In this case, that deletion is not very important for several reasons:

  • It’s just a row of LEDs. If the reconstruction looks reasonable it’s good enough.
  • The position of the other pad is still encoded in the zone information saved earlier to the Eco2.User layer.
  • The position can be reconstructed from the information saved from the Silkscreen into the Eco1.User layer.

Care and compromise involving speed, accuracy required, and experience are needed for this procedure.

For this PCB, parts of the old zone outline needing removal can be quickly selected with the u and i shortcut keys (or depressing the u key twice or thrice in KiCad V6) This expands the copper selection. Eg. selecting a single segment:

and then pressing u results in this selection:

At this stage in the reconstruction it also helps to turn off additional clutter such as clearance views. This is achieved through: Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outline: Do not Show

If small errors in the Gerber files show, such as track ends not ending in the center of pads:

they can be “repaired” by hovering over the track end and pressing d for “drag” then snap the track end to the center of the via,

before you delete the via that should be a pad.

After the cleanup the PCB looks like:

And with the information preserved from the silkscreen to Eco1.User turned on again:

Eeschema / Tools / Update PCB from Schematic

This is a normal step for any KiCad project. The PCB now looks like:

The main difference between this, and a normal workflow is that there is already a PCB outline and copper tracks in the PCB.
In this early stage, all the copper tracks are part of the “no net”. This can be changed in KiCad by simply placing a footprint in the right place. Copper that is then attached to the pads of that footprint, will automatically get the name of that net assigned.
Place the footprints.
It’s easiest to start with something identifiable. Footprints for a square QFN can be awkward unless the orientation can be obtained from the Silkscreen, or a real PCB on your desk, so, items such as those should be left until later.
U3 is an easily identified voltage regulator in TO92 format so that is the first located.
Information moved from the silkscreen to Eco1.User now becomes important, so this layer is turned on.

Zoom in around U3 in the north west corner of the PCB.

Place new footprints over the back-imported copper tracks.

Press t for Get and Move Footprint, type in “U3” or select it from the drop down box.

Place it on the existing tracks:

In the screenshot above, the red copper track on F.Cu has now been assigned to the “Earth” net because it connects to that pad.
When grabbing a footprint with t, its attachment point is the center of pad 1. In this particular case there is no straight correlation between pad 1 and the copper track, as the track goes right through the footprint. Pad 2 is a better choice, because a track ends in the footprint. Grab the footprint by pad 2, and move that footprint until pad 2 snaps to the end of the track. This can be recognize by the cross and circle that indicate that KiCad found a snap point.
To accomplish this, make sure that: Pcbnew / Preferences / Preferences / Pcbnew / Magnetic Points / Snap to Tracks is set to Always.

An important thing to emphasize is very little information is needed to re-create exact footprint placement… only the endpoint of a single track (to have a point to snap to) and which pad of the footprint to snap to that track end. This is why all the pads were deleted in an earlier stage. The information is just redundant.

As more footprints are being placed, KiCad expands the netlist information from the No net to the various nets of the schematic. In the screenshot below, KiCad already knows of the nets connected to three of the pins of connector J3.

In the next screenshot most of the footprints are located in their right positions.

After all the footprints are placed. there are still a few ratsnest lines left from pins which were connected directly to the GND plane. Deleting the remnants of the GND plane was probably the most time consuming step. A polygon of the GND plane has been preserved (moved to) the Eco1.User layer. Turning that layer on again reveals still a lot of internal geometry of the GND plane which was not needed.

Eco1 shows some other important information. The North west corner of this PCB does not have a GND plane. Because the outline of a GND plane (usually) is simple, the quickest method is usually to just draw a new GND plane. and then turn the Eco1.User we used as a reference off again.

This completes a good re-creation of a PCB by reverse-engineering from the Gerber files.

Further checks and Cleanup

Run the DRC: Pcbnew / Inspect / Design Rule Checker It is likely that the DRC will give some errors.
If the work has been accurate, most of the errors will be simple. Design rules and net class information have not been set up so the current PCB may clash with the default rules of KiCad. Fixing this is normal procedure and not part of this example.

It is important to note that as footprints are placed on copper tracks, the copper tracks assume the identity of the nets of the footprints. If DRC flags tracks that are going to pads as: Track too close to pad, then it is clear some error has been made, and this must be fixed.
There are several ways in which errors can occur. Most important at this stage is to realize that all the copper tracks are a direct import from the Gerbers. Not a single copper track has yet been drawn nor moved, so this should be the reference when resolving conflicts flagged by DRC.

Possible causes of Conflicts

  • Footprints placed wrongly so copper gets assigned to the wrong net.
  • Errors in footprints. All footprints are new, pads may be bigger and not fit, some pads may have slightly different locations (for example TO92 inline, or in a triangle)
  • Errors in schematic entry, which result in a difference between the imported netlist and the implicit netlist laid out in hard copper.