Reverse engineering KiCad project from Gerber files

  • 2021-09-06Txx:xx Work in Progress. Incomplete!
  • 2021-09-06T15:15 It’s fairly complete now. Time for something completely different. Some help with proofreading and finding missing or unclear parts is appreciated.

The goal of this reverse-engineering tutorial is to re-create a complete KiCad project from partial information. I assume the only information available is a schematic in some readable, (but not EDA form, such as a .pdf or a .png picture, and a set of gerber files.

In short, the steps are:

  1. Create empty KiCad project.
  2. Re-enter the schematic.
  3. Use KiCad’s Gerbview to create a PCB.
  4. Cleanup the PCB in Pcbnew.
  5. Assign footprints in the schematic, or with the Footprint Assignment tool.
  6. Eeschema / Tools / Update PCB from Schematic [F8]
  7. Place new footprints over the back-imported copper tracks.
  8. Use DRC to resolve differences and fix mistakes.

Schematic Entry

If only a picture of the schematic, or a schematic on paper is available, then it has to be re-entered in KiCad. Not much can be done about that. It’s still useful to have that information of course. There is a big difference between simple data entry or reverse-engineering data.

If a schematic in .pdf format is available (or if it can be converted to a .pdf format) then it may be possible to extract more information in a semi-automated method. For example uConfig is one of the many side projects around KiCad. It’s original goal is to extract data from datasheets and create KiCad schematic symbols. Not the same, but very similar to recreating schematic symbols from a schematic in .pdf format.
I have not used this (yet), and there may be other methods to do something similar (there are many side projects around KiCad)


At the moment, I simply re-use the schematic that was part of the project I used for this tutorial, as the steps are the same as entering any schematic in a KiCad project. (Except that data entry is quicker then designing a schematic).

Gerber Data Extraction & Cleanup

In KiCad’s Gerbview, there is the menu item: Gerbview / File / Export to Pcbnew (or Gerbview / File / Export to Pcb Editor in KiCad-nightly V5.99). And it does as the title says. It creates a PCB from a set of Gerber files. A disadvantage is that a lot of information is simply missing from Gerber files, but it is much better than re-designing a PCB from scratch, and it is a method that can be used with any program that creates Gerber files.

What you can “rescue” from Gerber files:

  • PCB outline & mounting holes.
  • All the tracks.
  • Footprint placement (Implicitly encoded in the ends of tracks).
  • Netlist (Implicitly encoded in the location of the tracks).

For the rest of this tutorial, I assume there is only a set of Gerbers, and a viewable schematic available such as a .pdf file or a printed schematic.

First step is to create an (as of yet) empty KiCad project from the KiCad project manager, and start expanding it:

  1. Open the project manager.
  2. Project manager / File / New Project
  3. I used “Gerber_Reverse” as the project name.
  4. Exit KiCad.
  5. Create a subdirectory “gerbers” in the newly created project.
  6. Copy all the gerber files there.
  7. Start the KiCad project manager again.
  8. Start Gerbview from KiCad.
  9. Load all the Gerber files: Gerbview / File / Open Gerber Plot File(s)

Now comes the export step:
Gerbview / File / Export to Pcbnew (KiCad V5)
Gerbview / File / Export to Pcb Editor (KiCad-nightly V5.99)

For the board file Name, use the same name as the just created KiCad project, which is “Gerber_Reverse”. If your newly created project already has a PCB file, then just overwrite it.

The “Layer Selection” has to be done right. A typical set of Gerber files has PCB outline, copper, Solder mask and Silkscreen layers, and it may have more, but those are not very important. The most important layers are the copper layer(s) and the PCB outline. Layers like Silkscreen and the solder mask are not very important, but can be used as a reference. For example, if it is ambiguous which copper layer is the top or the bottom, then this can be deduced from the silkscreen. For example, the silkscreen layer for the bottom layer is shown mirrored in the gerber files.

For this tutorial I only export 4 layers:
image
The two copper layers, PCB outline, and the Silkscreen layer. I export the Silkscreen to “Eco1.User” because I only want to use it as a reference (Why will become clear later).

Those were all the steps for Gerbview, and you can close it now.


Now open the created PCB in Pcbnew.
It’s a bit unfortunate I choose “Eco1.User” for the silkscreen export, because it has the same color as B.Cu. That’s easily fixed by double clicking on the colored rectangle and choosing another color for that layer:
image

Here is the result. All the info from the exported layers is there.

But it has a lot of obvious faults too.

  • There are no Footprints.
  • Pads have been replaced with via’s.
  • All drills are the same diameter (we did not export hole sizes).
  • There is no real information about zones. Just “painted copper”.
  • There are no texts (on the exported silkscreen) It’s just graphic lines in the form of text.

The next step is to cleanup information we do not want.
This PCB is relatively clean, because it was created with KiCad originally. Other Gerber file sets can create lots of small tracks, SMT pads and zones that are “painted” (That is, made from lots of small copper segments).

This PCB has a big polygon on F.CU:


This polygon may have some useful info, and therefore I move it to the Eco2.User layer (Select the polygon, press e for edit. Change layer to Eco2.User). Then hide the Eco2.User layer by removing the checkmark in the Layers Manager. image.

The edges of the real copper zones have been transformed to lots of small copper segments. This is useless info, and they can all be removed. For removing these, you can make good use of the box selection in KiCad. If you drag a box from left to right, then KiCad only selects items that are fully enclosed by the box. (This is handy for lots of small segments). If you drag a box from right to left, then KiCad selects everything that is in the box, and all items crossing the box boundaries. (This is handy for a reverse-engineered PCB that came from an old version of Protel. In that Gerber file set all copper zones were painted, and consisted of lots of long horizontal lines).
The cleanup is a bit tedious, but it’s not difficult, and goes relatively quickly with one hand on the mouse, and the other on the [Del] key.

Stuff to delete:

  • All painted copper. (both remnants from zones, painted SMT pads and more).
  • The via’s that have been created from the THT pads.

Stuff to keep:

  • Copper tracks.
  • PCB outline information.
  • Mounting hole information.
  • Real via’s.

Pay Special attention to:

  • Preserve track ends that end in pads. Track ends should end in the center of pads (both for THT and SMT), but this is not always the case. Not all track ends have to be preserved. The minimum is one track end for each footprint. The reason for this is that these track ends are used in a later stage to place real footprints on.

With these rules in mind, the cleanup can be done relatively quick.
For example, in this project there are three THT LED’s in the South East corner of the PCB:

(After turning Eco1.User off again, we want to reserve that info for reference later)
With this box drag from left to right:

resulting in this selection:

And a [Del] then results in:

So that is a cleanup for 3 footprints with a single delete. I did remove a little bit too much. The footprints were in line with each other, while the resulting track ends are not in line. A [Ctrl + Z] and showing via’s in outline mode shows why. The middle LED had a small track segment from the center of the track. (Highlighted in the screenshot).

In this case it is not very important for several reasons:

  • It’s just a row of LEDS. If the reconstruction looks reasonable it’s good enough.
  • The postion of the other pad is still encoded in the zone info we saved earlier to the Eco2.User layer.
  • The position can be reconstructed from the information saved from the Silkscreen into the Eco1.User layer.

It is quite possible to delete too much though. The decision of what must be preserved, and what can be deleted is a combination of the compromise between speed and accuracy you need, and experience.

For this PCB parts the old zone outline that must be removed can be quickly selected with the u and i shortcut keys, which expand a selection with copper that is already selected. For example, selecting a single segment:


and then pressing u results in this selection:

At this stage in the reconstruction, it also helps to turn off the view of the clearances. It is just clutter in this stage. So turn off Pcbnew / Preferences / Preferences / Pcbnew / Display Options / Clearance Outline: Do not Show

If you see small errors in the Gerber files, such as track ends not ending in the center of pads:


then you can “repair” them by hovering over the track end an press d for “drag” and then snap the track end to the center of the via, before you delete the via that should have been a pad.

After the cleanup it looks like:

And with the info preserved from the silkscreen to Eco1.User turned on again:

Eeschema / Tools / Update PCB from Schematic

This is a normal step for any KiCad project. The PCB now looks like:

The main difference between this, and a normal workflow is that there is already a PCB outline and copper tracks in the PCB.
In this early stage, all the copper tracks are part of the “no net”. This can be changed in KiCad by simply placing a footprint in the right place. Copper that is then attached to the pads of that footprint, will automatically get the name of that net assigned.
You can start with any footprint. It’s easiest to start with something identifiable. Footprints of a square QFN is not handy, unless you can identify the orientation from the info imported from the Silkscreen, or from a real PCB on your desk.

I start with something small, for easy (and small) screenshots. U3 is a voltage regulator in TO92 format. As we’re entering more info to the PCB now, and there is not much left on the copper layers, the information imported form the silkscreen to Eco1.User is now important, so turn that layer on.

Zoom in around U3 in the north west corner of the PCB.

Then press t for Get and Move Footprint, type in “U3” or select it from the drop down box.
image

Then place it on the existing tracks:


In the screenshot above, you can see that the red copper track on F.Cu has now been assigned to the “Earth” net, because it connects with that pad.
When you grab a footprint with t, it’s attachment point is the center of pad 1. In this particular case there is no straight correlation between pad 1 and the copper track, because it goes right through the footprint. Pad 2 would have been a better choice, because a track ends in the footprint. So grab the footprint by pad 2, and then move the footprint until pad 2 snaps to the end of the track. You can recognize this by the cross and circle that indicate that KiCad found a snap point.

To do this, make sure that: Pcbnew / Preferences / Preferences / Pcbnew / Magnetic Points / Snap to Tracks is set to Always.
An important thing to emphasize here, is that you need very little information to re-create exact footprint placement. All you need is the endpoint of a single track to have a point to snap to, and you need to know which pad of the footprint to snap to that track end. This is the reason we deleted all the pads in an earlier stage. The information is just redundant.

As you are placing more footprints, KiCad expands the netlist info from the to the various nets of the schematic. In the screenshot below, KiCad already knows of the nets connected to three of the pins of connector J3.

In the next screenshot most of the footprints are put on the right spots. Just a few left, outside of the PCB.

After all the footprints are placed. there are still a few ratsnest lines left from pins which were connected directly to the GND plane. Deleting the remnants of the GND plane was probably the most time consuming step. A polygon of the GND plane has been preserved (moved to) the Eco1.User layer. Turning that layer on again, reveals still a lot of internal geometry of the GND plane which we don’t need.:


But it also shows some important information. The North west corner of this PCB does not have a GND plane. Because the outline of a GND plane (usually) is simple, the quickest method is usually to just draw a new GND plane. and then turn the Eco1.User we used as a reference off again.

And there it is, a good re-creation of a PCB by reverse-engingeering it from the Gerber files.

Further checks and Cleanup

Now it is time to run DRC: Pcbnew / Inspect / Design Rule Checker It is likely that DRC gives errors. If you’ve worked precisely, then most of the errors will be of simple things. At the moment we have for example not set up any design rules and net class info. and the current PCB may clash with the default rules of KiCad. Fixing this is normal procedure and not part of this example.

It is important to note that as footprints are placed on copper tracks, the copper tracks assume the identity of the nets of the footprints. If DRC flags tracks that are going to pads as: Track too close to pad, then it is clear some error has been made, and this must be fixed.
There are several ways in which errors can occur. Most important at this stage is to realize that all the copper tracks are a direct import form the Gerbers. Not a single copper track has yet been drawn nor moved, and this should be the reference when resolving conflicts flagged by DRC.

Possible causes of Conflicts

  • Footprints placed wrongly so copper gets assigned to the wrong net.
  • Errors in footprints. All footprints are new, pads may be bigger and not fit, some pads may have slightly different locations (for example TO92 inline, or in a triangle)
  • Errors in schematic entry, which result in a difference between the imported netlist and the implicit netlist laid out in hard copper.
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