Remember the goal is to make the impedance between the bypass capacitor and the IC as small as possible. Since this impedance is most important at high frequencies, trace/lead inductance is especially worth avoiding. Therefore, the bypass cap gets placed as close as possible to the IC lead, and has vias placed as close as possible to this pad, connected to the power plane. In really sensitive/higher power designs you can even use multiple vias to reduce inductance.
So usually it’s [VIA]-[BYPASS PAD]-[IC].
I would also caution against putting vias too close to pads. In addition to tolerance from drilling, you also have to worry about the via stealing solder paste from the pad. This can be avoided to some degree by tenting the via, but now you have to worry about soldermask tolerance and drill tolerance to ensure the hole is really plugged. Easier just to move the via away from the pad slightly. 4mil or so is enough usually.
In what frequency range are your components working?
For the AVR microcontrollers I use (Upto 20MHz or so) I just slapped on some decoupling caps with relatively short wires and never had a problem with them (In this regard at least)
I have some experience with the “Blue Pill” boards from china, and though layout looks like barely adequate, and they have no decent GND plane they still “work”. I have not used it’s ADC yet. I’ve read on forums you can not get more then 9 or so noise free bits out of the ADC due to bad PCB layout, while with a better layout 11 clean bits should be possible.
The quality of decoupling gets more important if analog and digital is mixed, and also with higher frequency of the chips. Those GHz arm cores, DDR chips and FPGA’s are a whole different beast then some smallish uC.
“Info” from the internet is soo opinionated, and without hard data or real measurements (Just like this post) I’ve also read those opinions of connecting the caps directly to the pins, and place the via a bit further for “filtering” purposes, but don’t know what’s true of it.
Generally speaking lower impedance is better.
Shorter tracks have lower impedance.
Multiple tracks parallel also have lower impedance.
So for what I can get from your screenshot, I would both use 2 via’s and directly connect the capacitor to the uC pin.
For what I’ve read about Via-in-Pad, the trouble is with the cappilary action of the via which sucks away too much solder from the pad. Possible solutions are:
Don’t use them.
Use small via’s, so les solder is sucked in.
Have the via’s filled by your PCB Fab.
Expand the solder mask cutouts with the approximate volume of the via for those pads.
Another good reference is the " Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers" by Mark I. Montrose from the IEEE press. Chapters three and four give some practical advise on capacitor decoupling, trace layout and termination. Being from the IEEE press, it walks through the “why” if you want to underlying theory and real measurements.
I try to keep vias close to the pad and lead traces very short. Be aware that vias to the power plane may be lower impendace than a trace, as pointed out in the sigcon.com reference. Here’s one of my layouts for reference:
Thanks a lot for pointing me to all this further information! It seems, that there is no right or wrong regarding the placement while different opinions exist…
I will try to get my hand on this book but I could not find a free PDF of it online. Never the less they have the printed version in the library.
Frequency should not be a problem but I am using a digital isolators (ADuM1201) and in the AN-1109 application note for the board layout guidelines they deal in detail with the topic of EMI mitigation. That’s where I started to look into proper decoupling again.
This is excellent @Piotr, I have not seen this before. It lists the Montrose book, @HaLed’s first link and IEEE transactions as references.
Regarding @HaLed original questions, Figure 1D and Part 5 of @Piotr’s references are a great place to start looking.
I would not say it this way. I would suggest it is like selecting the acceptable trace width given the required current for that trace. It just has a few more variables to understand. If I have an IC’s switching rise time (from it’s datasheet), operating frequency, power draw, number of power pins and size of the PCB, I can come up with a capacitor decoupling array strategy. Understanding the fundamentals shown in @Piotr’s references is the difference between using rule-of-thumb opinions and engineering a robust design solution.
I wonder why previously my links were changed to rectangles (in source they were just lines) and now it looks my links are lines in source and in result. In both cases these are links to pdf-s.
And probably the same but modified:
Change 1 in ‘part_1’ in address to 2,3,4,5,6 to get the rest.
I found those time many, many pdfs googling for EMC, but these in my opinion are the best compendium of all EMC subjects.
The problem with current ICs is that even you use classic 74HC00 serie you can’t be sure if (to reduce production costs) they are not manufactured with smallest possible technology with the result that slopes are much faster than in the same circuit from the same manufacturer made decades ago.
I’m guessing totally out of my league here, but it seems unlikely there would be much of a die shrink for bog standard HC TTL.
First there is the room needed for the pads for the wire bonding. Then there are the output transistors which need to have a certain size for the drive current, and on top of that it needs to be compatible with 5V (max 6.5V even I think) which makes the 3.3V processes unsuitable.
Combine that with very simple chips with just a handful of transistors and a certain minimum size for cut dies to be able to handle them reliably.
Such changes could also introduce complexity and hard to find bus of insufficient decoupling if they’re used for repair and those logic families have both guaranteed maximum and minimum timing.
Recently I’ve been dabbing some toes into STM32. 3V3 I/O, (most pins 5V tolerant), but internally it runs on 1.8V to get to it’s72MHz. See upper right corner of Page 11 of the 117 page datasheet:
For me, emc is the bigger concern. I want noise to stay within the boarders of my card/unit.
The first FPGA card I did over a decade ago had a nasty oscillation on the 3v3 rail. It wasn’t due to a lack of decoupling but the wrong sort. I was using cheap and nasty Traco’s to provide isolated power and then some reference buck designs … a combination of poor input filtering contributed to the ringing. Did the design work? Yup 5kW FOC motor-drive on a bench but that was all it was meant todo. It wasn’t like it was marginal either.
These days after taking a number of units through EMi testing and the cost & time involved, I spend more time worrying about this. Plane shapes of different voltages do not overlap as this is a stray capacitance that bypasses any impedance. Caps are carefully placed to try to keep the noise local to the generation.
Decoupling is there to “decouple” any inductance on the rail to ensure the load received it’s needed charge when it requires BUT it also provides a lower impedance loop.
I like to have one layer solid ground plane. Then I place 0603 or 0402 decoupling capacitors close to the Vdd pins and link.the GND pads to the plane with vias. The ground plane is a much lower impedance than the Vdd tracks.
I rarely have enough layers for a Vdd plane
I completely don’t know the internal IC technology, but can imagine that very old ICs can have so big dies that after 20…30 years die shrink can give enough cost save to be legitimate to perform specially that competitor manufacturers offer them cheaper and cheaper.
We have got into that trap about 10 years ago but not with standard HC but with small serial EEPROMs. In our educational microprocessor system (designed in 1995) we had several attachments. They were connected by 10cm flat cable. One of them contained serial EEPROM. It worked well till about 2010. Suddenly stopped. The EEPROMs were exactly the same from the same manufacturer but with the current delivery. The problem was slopes of EEPROM output being too fast end crosstalked to clock line.
E2 and Flash are unusual cases where a lot is going on at internally generated power supply voltages using charge pumps. This allowed some true die shrinks by thinning gate oxide and dropping these supplies
HC TTL is also an unusual case because there are so few transistors in them that the die size may be dominated by the pads for the bonding wires. Even a simple EEprom probably has 2 orders of magnitude more transistors, and less pads for bondwires too.
Also, for me, anything that goes trough a connector and off board needs extra attention. EEproms are often used on PC monitors too. There are 3 wires dedicated on a VGA cable for them. SDA, SCL and +5V, so a PC can read out EDID data even when the monitor is turned off or even unpowered.
But then again. A proper I2C EEprom has slew rate limited outputs. so a meter and a half of shielded cable should be no problem.
Anecdote:
Recently I had a peek at the service manual of the PM2534 which is an old Philips Benchtop DMM, and it makes a lot of use of I2C. Each chip has 100 Ohm series resistors in the I2C lines for damping, but for a benchtop DMM all the little things add up.
Ask your PCB assembly house about vias in pads. They might not like it because it will suck the solder from the via and lead to bad solder joints.
If you are soldering by hand you can just put more solder on it and get a decent joint.
Best is to avoid it. place the via so far from the pad that there is no overlap and the via will be covered by the solder mask.
