[Solved] Pad and Copper Fill Not Connected

Layout
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I am also guessing that you have a bunch of islands on this PCB. The routing of your tracks cuts the GND planes into a lot of pieces.

I would have expected that would get rid of at least a few of the (presumed) islands, but just throwing on a grid of via’s is far from ideal. Also, did you re-generate the zone boundaries (with b) after placing the via’s. I’m not sure if the via’s are recognized by DRC otherwise.

What do you think of this yourself. Can you see why KiCad marked it as unconnected / island?

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I’ve seen the occasional spurious Unconnected error in the DRC . . . never been able to re-create them and they have usually resolved themselves.

As I’ve not been able to reproduce the errors I can’t say for sure what fixed them . . . but I would try the following:

  • Update the PCB from the schematic
  • Re-fill the pours
  • Save all KiCad files, close all KiCad files and restart KiCad.
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jmk: What do you need? A screenshot of the board? The project?

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Thanks. I understand the island issue, but why would one of the errors be that an SMD pad is not connected to the GND pour right next to it when it has extended the pour to the pad as part of the filling process?

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It is set to “always”. So that means I don’t have an island problem, right?

Screenshot 2024-01-25 093725
Screenshot 2024-01-25 093725885×627 29.2 KB

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I tried all three of these - still have the unconnected errors. Worth a try though! :slight_smile:

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KiCad does not know what the “main” part of a net is. If KiCad detects that not all pads in a net are connected to each other, it just takes a random pad of that net and puts that in DRC. When hunting for islands, it does not help to zoom in and post screenshots to show that a pad is connected to some part of a copper zone. Do it the other way around. Take two pads which KiCad shows as “unconnected”, and then try to follow the copper from one of those pads to the other.

Also, connections though thermal spokes can be troublesome. KiCad has: PCB Editor / file / Board Setup / Design Rules / Constraints / zone fill strategy / Minimum thermal relief spoke count By default it is set to 2, but I am not sure whether KiCad accepts it if one spoke goes to a zone section on the left, and the other zone section is on the right, and if that is the only connection between those parts. I spent a few minutes to make a test, and KiCad seems to accept this without complaining:

image

Also, overall you have made a maze of your PCB. Using horizontal tracks on one layer and vertical tracks on another layer was a very common technique … 40 years ago. In these modern times and with EMC regulations it is much more common to have one or more layers dedicated for a GND plane, and then do as much routing as possible on another layer. For a two layer boards it often is not possible to keep all routing to the other layer, but cutouts in the GND layer are kept to a minimum. (Preferably never longer then 5 to 10mm)

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Thanks. I have it down to three errors. I can see an unbroken copper pour between the problem via and the problem pad. The problem pad has four thermal spokes.

But then I have the other error that says Zone [GND] on B.Cu is not connected to Zone [GND] on F.Cu, yet I have multiple THT that are ground connections with thermal spokes to both fills. Clicking on either one in the DRC Control dialog highlights the fills spanning the entire board.

Screenshot 2024-01-25 103519

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OK I solved it. I had the GND net hidden. When I turned it on it showed three unconnected GND points that were nowhere near the errors being reported and didn’t involve the via or the pad being reported. They were trivial to fix and now no errors.

So I would put this down to:

  1. User error forgetting to re-show the GND net

  2. KiCAD’s errors in this case were not pointing to the right locations, i.e. the information in the DRC Control dialog didn’t match the information in the ratsnet display

Thanks for the help.

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24

No.
Islands being not connected to any pad are deleted.
But if you have 10 islands and each of them is connected to a footprint GND pad they will not be deleted even they are islands having no connection between them.

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This may have been enhanced after v6. I have also proposed a logical solution for this split net error message problem, but it hasn’t been implemented. See pcbnew: DRC - unconnected pads should not be shown as pairs (#7416) · Issues · KiCad / KiCad Source Code / kicad · GitLab.

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@paulvdh I tried your suggestion - ripped out all of the tracks and started again. I got 90% of the way through but it was just becoming and bigger and bigger tangled mess. Yes I had less interrupted ground pour on the bottom but it really looked more like the rats nest on top.

Is there a book you recommend for learning different PCB layout styles?

Thanks.

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For dual layer PCB’s (with a decent GND plane), footprint placement is a very important step. It is also a puzzle, and there is no guarantee there is a solution to the puzzle. It takes some practice to do this. After you have done some 5 to 10 PCB’s you develop some experience and a sort of intuition for things that do and do not work. It’s not great if the tracks on the top side looks like a mess. Often it is an indication of bad footprint placement. However, if you have several parts with a high pin count, then footprint placement can’t fix this, and routing will always be a bit messy.

On one of your first screenshots (with the yellow hand-drawn line) I see quite a lot of tracks coming from “below the screenshot”, to “above the screenshot”. Why are so many tracks crossing all over the PCB?

Another (partial) solution is pin swapping. Often pin functions on microcontrollers, programmable logic and connectors can be re-assigned to make routing of the PCB easier.

Some people don’t bother to do 2 layer PCB’s. 4-layer PCB’s are much easier to route and they rather pay a bit extra for the PCB instead of spending the time and effort for routing it on 2 layers.

Another big issue is whether it’s just a hobby project, or if it’s commercial and it has to conform to EMC regulations. But even if it’s for hobby, attempting to do it “properly” will improve your PCB’s (and skills) over time.

I don’t have any recommendation for books Rick Hartley (From Youtube / altium) has made a bunch of good video’s. Especially his 2 hour long video about the importance of GND planes is worth watching (That is how important GND planes are). There are some more good youtubers, but mostly it’s practice to build up some experience. It’s also a skill that is for some people much easier to learn then for others.

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For 35 years doing pro SCH/PCBs; with my work :

  • about 50% of time is spent just placing parts. That takes experience to know how much room you will need to route say 12 differential pairs and control logic between one chip and another …

That stage is the hard part. Because everything you do there has influence on everything else.

  • the other 50% of time is routing traces, and a bit of pushing and shoving. Routing is fast and takes ‘no time’ with productive tools, unless you end up moving alot of stuff (because you got stuck !) , and then well, its a placement issue…

It’s all a matter of compromises. That’s what PCB people get paid for, the stress of making continuous compromises.

Always take a step back from routing and placement if it starts to get a bit of a mess. Often there are several solutions but you may not choose the cleanest placement solution first time.
Some designs are easy to route, and you pretty much end up routing them as they are drawn .

When I generate schematic parts (libraries) , I draw the symbol as the device is packaged where possible. I rarely draw by function . This is certainly the case for anything not BGA. This helps me choose pin locations early and avoid a rats next later, because layout faces you in schematic.

For routing topology / layers - some designs as I said will lend them selves to being laid out as they are in sch. In those cases, I expect the copper on the back to be ground, and to need to odd jumper here and there to get around. Run your power bars first and expect to use more decoupling ‘filter’ caps around the board because your power rails might have to take circuitous routes.

If the design has alot of traces going everywhere. say if you use every pin on a QFN32 or bigger micro, then I would suggest sticking to something like vertical top layer, horizontal bottom layer. Except on the fan out getting out of the chip, which is likely top layer, you must brutefully and without hesitation or resistance, stick hard to the vertical-top, horiz - bottom (or whatever you chose) . Remember - thu-vias (“PTH”) are free - for a fabbed board they cost nothing so use them.
You can find yourself hosed on ground room on back side quick.
***So in this case, be sure to place ground and power bars first (run them as layers of a highway in a group) . place them next to each other so you can drop decoupling caps across them at regular intervals to keep the supply rails low impedance and quiet . You can do very well with this method.

If you find the ground pours on the rear getting swiss-cheesed, pour a copper pour on the top side as ground and then do what you can do to stitch up the broken and isolated areas on the bottom side with the top side .

If the speed or EMI requires it, then 4 layers is a cheap choice.
Relax the inner layer clearances to at least 0.4mm or 0.5mm. That requires a layer-wise rule setup for clearances… If you run limit clearances on the inner layers you will pay for it in yield or reliability or price.

It’s a good idea to try and equalize copper on top and bottom so be sure to do a ground pour on top and bottom. I’d suggest settign clearances for these pours to at least 0.5 perhaps 0.6 mm , This will reduce or eliminate board warpage in reflow (since lots of copper on one sides expands one side and warps the board) …
Geez I can go on and on.
-glen

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29

Wow thanks Glen and Paul! That is great advice!

In regards to why I have lots of vertical tracks - for this board it has a bunch of connectors and I started by laying them out in a way that makes it logical and easy for the user. I.e. thinking along the lines of a “product”. I then tried to keep all analog signal conditioning together on one side of the board and all digital with MCU on the other. Unfortunately that led to needing to route some tracks from one side of the board to the other.

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digital one side and analog the other wont buy you any signal isolation whatsoever. so you might as well put it all on one side and make it easy to load the board instead of two stencil and two reflow cycles. if noise is an issue, then consider a 4 layer. the incremental cost of a 4 layer board is peanuts.

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I would suggest to read the articles I have linked here 3 years ago:

and here:

They are not on different PCB styles but about ‘the only one right style’ :slight_smile: .
In my opinion reading them are enough for 95% of PCB designers (the 5% I left for extra high frequency designers).

Almost all my PCBs are 2 layers. I always at bottom have full, continuous GND. My PCBs are not very complicated. Placements takes me may be even 80% of time. If placement is good then routing is very simple task when you accept that you don’t care how exactly tracks are routed. At the end you cen do some dragging to get them looking better.
During placement I switch the GND connection lines visibility off as these are connections I need not to take care of them as GND I have everywhere one via from me.
The example of such designed PCB:

At top right corner of microcontroller (IC in center) at VC net there is 0R jumping over 3 tracks. At bottom right corner there is 0R jumping over 2 tracks.
You could suppose that 0603 going from VC net to IC on the right is also 0R but not. I prefer to supply all ICs by their individual ferrite beads and it is it. I also prefer to have at any digital output the 47 to 100 ohm resistor close to the output pad. Thanks to that IC switching the output stage has to get from its supply a strong current pulse only to reload its internal capacitance and pulse needed to reload the rest of net is spread over time making generated EM noise smaller. These resistors and these ferrite beads helps a lot in routing. See 4 resistors on the way to IC right-down from microcontroller. In that microcontroller (AtXmega) I don’t have big flexibility in swapping pins. But as I had there this resistors I could just used them to unravel tracks. To the left there are over 20 0402 resistors having just the same function, but 0402 don’t allow me to go with track under them.
Any via you see at this PCB is GND. Even top-left of microcontroller you see something that looks like track starting and ending with via. It is also GND - I decided to make something like shield between data lines and control lines (pulses at data lines don’t cares as they are read in certain moments, pulses at control lines (like reset) cares much more).

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Good advice from Piotr. especialy on source R damping .

Yes, suggest staying with 0603 and 0805 unless you have a compelling reason to you 0402.
On your PCB , I do not seen any reason to use 0402.
As Piotr says, you give up being able to run a atrace under Rs and Cs when you go 0402.

All 0402 placement has to be under a microscope, or a decent machine. Many chinese PnP machines will not pick and place them, and even the pro machines will spit them out regularly with bad pickup.

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That suprises me. I’ve hand built many prototype boards that have 0402 parts. I don’t like to do it but I manage fine with just tweezers and magnifier glasses and a light. No failed boards.

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yes magnifiers , thats right. microscope, magnifiers same thing.