Decoupling capacitor via placement

I didn’t read that book but I suppose you can replace it with:

I think it is enough for most pcb designers.

This is a lot. Thank you for sharing this. I couldn’t find them online as well.

I can also share links for article series about EMC design not directly aimed at pcb design but don’t know if KiCad forum is right place to do that.


I see no harm! I’d enjoy reading it, it’s important material.

This is excellent @Piotr, I have not seen this before. It lists the Montrose book, @HaLed’s first link and IEEE transactions as references.

Regarding @HaLed original questions, Figure 1D and Part 5 of @Piotr’s references are a great place to start looking.

I would not say it this way. I would suggest it is like selecting the acceptable trace width given the required current for that trace. It just has a few more variables to understand. If I have an IC’s switching rise time (from it’s datasheet), operating frequency, power draw, number of power pins and size of the PCB, I can come up with a capacitor decoupling array strategy. Understanding the fundamentals shown in @Piotr’s references is the difference between using rule-of-thumb opinions and engineering a robust design solution.

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About 2004 I found an interesting serie of EMC articles by Keith Armstrong (for many years I didn’t know if Keith is a woman or men name). Later they became no accessible, but when I tried to find them few years ago I found them once more:

I wonder why previously my links were changed to rectangles (in source they were just lines) and now it looks my links are lines in source and in result. In both cases these are links to pdf-s.

And probably the same but modified:

Change 1 in ‘part_1’ in address to 2,3,4,5,6 to get the rest.

I found those time many, many pdfs googling for EMC, but these in my opinion are the best compendium of all EMC subjects.


The problem with current ICs is that even you use classic 74HC00 serie you can’t be sure if (to reduce production costs) they are not manufactured with smallest possible technology with the result that slopes are much faster than in the same circuit from the same manufacturer made decades ago.

I’m guessing totally out of my league here, but it seems unlikely there would be much of a die shrink for bog standard HC TTL.

First there is the room needed for the pads for the wire bonding. Then there are the output transistors which need to have a certain size for the drive current, and on top of that it needs to be compatible with 5V (max 6.5V even I think) which makes the 3.3V processes unsuitable.
Combine that with very simple chips with just a handful of transistors and a certain minimum size for cut dies to be able to handle them reliably.

Such changes could also introduce complexity and hard to find bus of insufficient decoupling if they’re used for repair and those logic families have both guaranteed maximum and minimum timing.

Recently I’ve been dabbing some toes into STM32. 3V3 I/O, (most pins 5V tolerant), but internally it runs on 1.8V to get to it’s72MHz. See upper right corner of Page 11 of the 117 page datasheet:

For me, emc is the bigger concern. I want noise to stay within the boarders of my card/unit.

The first FPGA card I did over a decade ago had a nasty oscillation on the 3v3 rail. It wasn’t due to a lack of decoupling but the wrong sort. I was using cheap and nasty Traco’s to provide isolated power and then some reference buck designs … a combination of poor input filtering contributed to the ringing. Did the design work? Yup 5kW FOC motor-drive on a bench but that was all it was meant todo. It wasn’t like it was marginal either.

These days after taking a number of units through EMi testing and the cost & time involved, I spend more time worrying about this. Plane shapes of different voltages do not overlap as this is a stray capacitance that bypasses any impedance. Caps are carefully placed to try to keep the noise local to the generation.
Decoupling is there to “decouple” any inductance on the rail to ensure the load received it’s needed charge when it requires BUT it also provides a lower impedance loop.

I have some links I’ll post later.

I like to have one layer solid ground plane. Then I place 0603 or 0402 decoupling capacitors close to the Vdd pins and link.the GND pads to the plane with vias. The ground plane is a much lower impedance than the Vdd tracks.
I rarely have enough layers for a Vdd plane

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I completely don’t know the internal IC technology, but can imagine that very old ICs can have so big dies that after 20…30 years die shrink can give enough cost save to be legitimate to perform specially that competitor manufacturers offer them cheaper and cheaper.
We have got into that trap about 10 years ago but not with standard HC but with small serial EEPROMs. In our educational microprocessor system (designed in 1995) we had several attachments. They were connected by 10cm flat cable. One of them contained serial EEPROM. It worked well till about 2010. Suddenly stopped. The EEPROMs were exactly the same from the same manufacturer but with the current delivery. The problem was slopes of EEPROM output being too fast end crosstalked to clock line.

E2 and Flash are unusual cases where a lot is going on at internally generated power supply voltages using charge pumps. This allowed some true die shrinks by thinning gate oxide and dropping these supplies

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HC TTL is also an unusual case because there are so few transistors in them that the die size may be dominated by the pads for the bonding wires. Even a simple EEprom probably has 2 orders of magnitude more transistors, and less pads for bondwires too.

Also, for me, anything that goes trough a connector and off board needs extra attention. EEproms are often used on PC monitors too. There are 3 wires dedicated on a VGA cable for them. SDA, SCL and +5V, so a PC can read out EDID data even when the monitor is turned off or even unpowered.

But then again. A proper I2C EEprom has slew rate limited outputs. so a meter and a half of shielded cable should be no problem.

Recently I had a peek at the service manual of the PM2534 which is an old Philips Benchtop DMM, and it makes a lot of use of I2C. Each chip has 100 Ohm series resistors in the I2C lines for damping, but for a benchtop DMM all the little things add up.

I don’t remember if we had a problem with I2C, MicroWire or SPI EEPROM. There were all of them in the EEPROM demo set.

Ask your PCB assembly house about vias in pads. They might not like it because it will suck the solder from the via and lead to bad solder joints.
If you are soldering by hand you can just put more solder on it and get a decent joint.
Best is to avoid it. place the via so far from the pad that there is no overlap and the via will be covered by the solder mask.

I was working on a project for a previous employer where someone else in the collaboration had designed some LNA (preamp) boards for some PMTs being used as individual pixels for telescope cameras. The board designer had used via in pads w/o any apparent mitigation for solder starved pads. I (and my team) ended up hand reflowing over 2000 boards to get more solder on the pads due to an extremely high failure rate of the boards. So, please take care when using via in pads for the sake of the poor people who need to integrate your boards into a working widget.

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Please keep in mind that those pages recommending individually connecting the pin and cap to the planes with separate vias are both making one critical assumption that does not apply to 99% of PCBs - that you’re using filled and plated laser-drilled microvia-in-pad. The text stating that that approach gives the shortest path and lowest parasitic inductance is ONLY true for boards manufactured under those conditions. For standard boards using mechanically-drilled and open vias that are separated from the pads in order to prevent solder wicking, that’s simply not true, and using two individual vias to connect the decoupling cap and pin to the plane will do nothing but push the cap further away from the pin and increase the parasitic inductance between them.

Also keep in mind that for the vast majority of components, it won’t make any difference either way. For components where it does make a difference, just follow the datasheet recommendations (which will usually have the cap and component on the same side of the board located very close to each other with a wide trace connecting them).

I was working on a project for a previous employer where someone else in the collaboration had designed some LNA (preamp) boards for some PMTs being used as individual pixels for telescope cameras. The board designer had used via in pads w/o any apparent mitigation for solder starved pads.

Sounds like it was meant to be fabbed with filled and plated vias, but someone forgot to tell the company doing the board fab. As with a lot of other aspects of PCB design, that kind of thing isn’t covered by the design docs coming out of the CAD software, it has to be separately communicated to the fabricator (along with copper thickness, impedance/stackup requirements, etc.). The designer should have included a separate document for the fabricator with these kinds of instructions, but maybe it got left out somehow. Either way, yes, if you’re doing via-in-pad, you need to either assemble the boards by hand where you can compensate for the vias wicking away solder, or you need to use filled and plated vias.

Still one note. When the manufacturer talks about “via in pad” it most probably means the special technique where the via is filled and/or covered with copper so that you can’t necessarily see it at all. A normal via in a pad isn’t called “via in pad” and isn’t anything special.

For example in pcbway order page you can choose “Via in pad/ Via filled with resin” option. Try it with 50x50mm standard board. 10 pieces without that option: $5. 10 pieces with that option: $260.

But if you just add a normal via in a pad and order without via-in-pad they’ll happily make it for $5 and the via is not filled/plated.

The KiCad default via of 0.8/0.4 mm is large and the hole swallows solder.
The low cost fabs can deal with 0.6/0.3 mm, which behaves far better without resin fill