In release notes I did not find any information regarding this so I guess this feature got postponed. I would like somebody to confirm this to me. Also do you have any information whether some newer workaround is available on this issue?
I doubt that this is possible on a footprint level, but someone else may have a idea.
OT: Are you sure you want to use a net tie? What do you want to connect with each other and are this tracks or planes?
Net ties may cause more EMC problems.
I have PCB with 4x MAX11270 ADC and currently I am trying to figure out best way to connect them (seperating digital ground GND_D and analog ground GND_A).
On my reddit post where you can find the schematic I got a tip that I can create seperate GND_A for each ADC and seperate it from GND_D using net tie. So currently I am playing with this idea:
Please take note that all spilled ground planes+net ties should be located in inner layer while ADCs are on top layer.
seperating digital ground GND_D and analog ground GND_A
Don’t do that, this is bad for EMC. You basically create a dipole antenna this way. Use a single GND whenever possible, especially when your circuit contains CMOS digital logic (basically every PCB with a IC on it).
With different GND-planes, Your MAX11270 ADC basically becomes a RF transmitter and uses the GND_A and GND_D as 2 parts of a dipole antenna.
What you should do instead, is separate the signal tracks of each section to its own region on the PCB. For example: Analog 1 on the top left, Analog 2 on the middle left, Analog 3 on the bottom left, digital on the right… (or whereever you want them to be). Or like the rest of what toybuilder said, which is correct:
You want to avoid routing any analog signals around digital signals. Where digital signals originate at the ADC, place the signals so that they launch away from your analog signals.
Your analog signals are not one monolithic entity – so it’s ok to separate them into self-contained analog sub-circuits if you need the analog stuff to be at different parts of the board.
I also wanted inner-layer copper on ties, but it was a rabbit hole of rules and such. I just created a power-plane tie of my own with PT holes that overlap – it throws drc errors (which rules could eliminate I am sure) but I don’t care to get too fancy. All layers nicely tied. I used three holes 'cause I liked the techno-lego look, but two holes would suffice.
Yes, you absolutely will benefit from a split digital/analog plane, but not the way you showed with four netties into different parts of the digital plane. You can likely have one analog plane for all four adcs.
You want one big nettie at the point closest to power supply ground, and fan out analog and digital from there. If you connect your nice clean adc plane to a noisy part of the digital plane, it is like adding a noise source in series with the analog return – you want the analog return connected as close to the power supply point as possible. This is one of my adc layouts – this one measures voltages down to one microvolt, and that would not be possible if the digital crap got into the analog plane at all. Three fat netties straddle AGND and DGND and the planes split under the adc.
Also, do you really need four adcs? Have you looked into multi-channel adcs? Many just have a goofy mux on the front end, but I have had great success with ti’s simultaneous-sampling ads12xx family, which have multiple adcs and not just a mux. Parts like ads1274, ads131m04, or ads131e04, come to mind.
Yes, you absolutely will benefit from a split digital/analog plane, but not the way you showed with four netties into different parts of the digital plane. You can likely have one analog plane for all four adcs.
No. This only works when your digital technology doesn’t produce step edges. Means you can’t use CMOS logic (virtually all digital and mixed ICs that are designed in the last 40 years).
Spiting grounds are a common reason for failed CE testing, because this PCBs will radiate more.
this one measures voltages down to one microvolt, and that would not be possible if the digital crap got into the analog plane at all.
You can achieve the same with a single plane, but with the analog and digital tracks far away from each other.
If you want to have different planes, use different power supplies as well and use optocoupler to transmit data in between.
My understanding is that when a signal crosses the underlining split planes the return current of high frequency parts of the edges tries to stay just under the track. Since it encounters a wall it spreads on the plane on its side until it finds the infamous “star point” and then it can cross to the other plane sourcing the signal.
What happens if you join the split planes with ties under every crossing signal on the top side? Could it work?
My understanding is that when a signal crosses the underlining split planes the return current of high frequency parts of the edges tries to stay just under the track. Since it encounters a wall it spreads on the plane on its side until it finds the infamous “star point” and then it can cross to the other plane sourcing the signal.
That is one of the possible problems. If you must split planes, never cross a track over it. But even when you don’t cross track, there is still a risk you have too much EMC radiation.
What happens if you join the split planes with ties under every crossing signal on the top side? Could it work?
At some point you will end up with a single plane with some gaps in it (which you will have anyway, since you place vias and THT-pads that create holes in the plane). But from a signal point of view, this holes are not there except they are large (at least a few mm in at least a single direction).
Look there is only a risk, if you want to gamble, you can split ground planes. It will probably still work but may or may not fail EMC testing for CE or other regulations.
What are your requirements regarding EMC regulations?
I am another poster, it was just out of curiosity.
Actually I started another thread because I’m all for one big ground plane and my problem with kicad is that you cannot have two different netclass zones overlapping. I have a power class with big tracks and vias and another with smaller and I want all to go to the same layer with the big one gnd copper plane. Any ideas how to solve it?!
Well I have had great success with split-plane designs, with fcc/ce testing. If your design layout and testing led to single planes passing, I can see how that careful layout would pay off.
I agree that signals should never cross ground planes – that is a sure ticket to emi issue, and that analog and digital should have different supplies – even an analog power pin on a micro should be fed via a ferrite bead if it must use the same supply as the digital side. I use ferrite beads all over the place.
I was reading about joining split planes in such places with some pF capacitors. The idea was to give a short way for high frequency signal edge components that are the source of EMI while at the same time keep working frequency currents to use star-like ground to have control of unwanted influence of one of them on another.
In the years 2002-2006 I was reading a lot about EMC so I’m not sure if it was in mentioned papers that I remembered as the best in this subject I have ever read.
