It will be possible to create different types of net ties in the future – they won’t all have to look like the ones in the current KiCad libraries with two pads connected by a polygon. However, they will still need to involve footprints or pads – it won’t be possible to select a track segment and make it a net tie.
I thought the plan was to make them “first-class citizens”, i.e. a “thing”. It would be a separate entity in the schematic, but a track or a via could work as a net tie in the layout: https://gitlab.com/kicad/code/kicad/-/issues/2018. Or do you mean just that?
Well, first of all that issue needs to be split and updated, as it covers a bunch of different concepts, and these days we want issues to be more narrow in scope. So, I won’t cover star routing and decoupling capacitors.
A track or via is not a good candidate to be a net tie in KiCad architecturally, as Paul said. Technically it would be possible with a standalone via, so we could look at adding that at some point.
The “first-class citizens” thing is about defining net tie behavior more formally rather than looking for the net tie keyword in a footprint and then changing how that footprint is treated. The current plan is still that net ties are defined around pads (one or more pads that are allowed to form shorts between nets). The implementation detail of how this will be handled in the schematic is still being figured out, but at the end of the day, they will still be symbols and footprints, not some new kind of object. Net ties will just make use of some new features added to symbols/footprints (kind of like how alternate pin functions were added in V6).
Is the “Group” thing in KiCad-nightly a good candidate for formalizing net ties?
Something like a footprint with some pads and a polygon inside a group, and when you enter the group, you can move the pads and modify the polygon to suit a particular situation.
For me it does not matter much. I am used to managing my own libraries when needed and modifying footprints to fit particular situations.
I don’t think the formal implementation will be related to groups. You could certainly make a group inside the footprint if you wanted to, but the formal net tie specification (Pad 1 and 2 form a net tie, for example) will not involve groups. We want to support “single-point” net ties, but it’s not yet clear if we will do that using a single pad, or multiple pads stacked on top of each other.
RIght now it’s a limitation of the current system that the net tie footprints have to use two pads connected by a polygon. When we remove that limitation, if you wanted a specific shape for your net tie that is specific to a design (rather than being stored in a library) it would probably make sense to use a minimal-size net tie (like, a single pad that is the same size as the track width you are using) and create any “extra shape” on the board rather than in the footprint.
So does that mean that I am missing the polygon? I used a “line” and not a polygon. A week or two ago I searched FAQ for how to implement a net tie and did not find it.
One quirk of mine is that I pretty much use only my own footprints. “NIH” (That is not the National institute of health) is the rule! 
Being able to join nets at a single point is a good idea, but I hope it will not be the only solution.
I like the separate pads + polygon in the aspect that it adds physical separation in a way that is specified in the footprint itself.
For example, the feedback point of current sense resistors can not sprout off in a random direction. If that has to be done by locking track segments it will be a step backwards.
Also related to this, are footprints that consist of copper tracks, such as printed inductors, antenna’s and RF things such as in the “microwave toolbar”.
In the latest Ucamco Gerber specification, I read that such items can have their own layers and definition in Gerber files.
A line should work also. You just need net tie at the start of the footprint keywords field.
I am talking about additional ways to do net ties, not getting rid of the current way.
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Sounds good; thanks.
Could you please let me know what for practically are net ties used.
I have never used any.
Later in thread the RFID antenna is mentioned. When I needed to do one I just had no time for experiments and I have done it as one net (routing tracks as I needed). I think tracks are not allowed in footprint so I thought it will be simpler just to route it and not try to define footprint. But from reuse point of view it would be better to have footprint for it.
I am in 5.1.10.
NET Tie user’s case:
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Hi, Piotr
I do not want to compete with the Altium documentation but it seems to be pretty Altium specific. I think that the net tie is very useful but not essential. My argument is my opinion and is somewhat complicated:
- Perhaps the main use is for connecting different grounds such as power ground, analog ground, and digital ground.
1a) This could be done with a 0 ohm jumper but the net tie is more versatile and avoids needing a physical component.
1b) Defining separate grounds is not essential but it is the BKM (best known method) of describing the interconnection of grounds when you want to separate noise generators from noise sensitive parts of a system. A pcb layout person could keep all of this in her/his head and do it manually with only one ground, but then the requirement is not documented and errors seem more likely.
2a) Net ties are also useful where you need to control connection points and net classes. Many times I have seen a “silver box” power supply which produces 100 - 200 Amps of output current. The output connectors are large (1 cm?) diameter brass or copper machine screw stud. But also connected to those studs are suitable large diameter ring terminals crimped to small gauge wires (such as AWG24?) which is the output sense wire. Whereas the main output current is >100 Amps, the sense wire might handle 1 mA or less. The output and sense wire are both connected together; should they be the same net? Will you use a 100 Amp net class rule for a sense wire which is carrying 1 mA? Placing a net tie between the output and the sense wire resolves that question by allowing the interconnection of an output power net to a sense net.
- I will bet that other members of this forum will have different answers…
- Kelvin taps for the likes of sense resistors
- wanting to assign two netnames to a signal net, especially heirachical sheets
- need to change netclass rules: track width for main conduction path, clearance due to HV
Net-ties are a hack in every single eCAD I have ever use and the fact they are a footprint limits their placement to F.Cu or B.Cu. being able to place on any layer would be ideal.
Now Mentor do have a net Alias where you do something like foo|bar to provide the alternative name at a junction (main branch is foo)
Likewise Mentor does have this nice thing called “net ordering” which can help in identifying what part of a stub is where, handy if you fork a signal and you need equal lengths (IE clock distribution)
In KiCad 7, footprints won’t be restricted to the top / bottom layers in this way.
This kind of net topology feature has also been discussed (separate from net ties) - it’s also relevant for signal integrity rule checking, length matching, etc
Thanks.
I start to see why I have never had a real need for net-tie. After reading a series of EMC articles (I gave here at forum links few times) I took as my method of having one continuous GND and just separate disturbance source and victim in space. It is also important that I practically do not use analog components.
My classification:
1mA - small current,
50mA - typical current
200mA - big current
1A - huge current
I got it. Till now I didn’t noticed how Class default track width is used. It seems to me that when I press ‘X’ I always start with width selected in box top-left of screen.
Thanks.
Didn’t tried it but didn’t you get that by just placing two net names at connected wires?
OK. I think I got it. With net-tie you will probably have separate net names at tracks and pads in separate places at PCB. Never had such need.
I understand track width but clearance ??? If you connect two nets with net-tie they will both have the same voltage.
I have to experiment to find how to use default track width for Class.
I specify as default 0.25mm. But I also specify 0.2mm , 0.4mm, 0.7mm,… The effect is KiCad places 0.25 at top of list and when I try to switch width using W/Shift-W I am each time surprised width are not changed monotonically. Is there any solution to it other than assigning 0.2mm as default?
Think 5.1.x for now as 5.99 offers a rich language for rules
Clearance rules are EXTREAMLY crude… A netname added to a class. So imagine a high voltage case where your DC+ or DC- needs 3mm clearance due to IPC2221 … Great the present kicad permits this nicely. But once you place anything referenced to DC-, say a voltage sense circuit (low-side high voltage divider feeding opamp/adc…), Every net that is DC- inherits this clearance so now try to track 0402 resistor (1206 as part of the main divider ) and/or a SOIC8 … you can’t. All you can do is place a net-tie to then provide a new netname and thus net class rules. you might still get a DRC violation if the two pads of the net-tie that are closer that the clearance rules but it’s a small price to pay
I have not tried with 5.99 and the rules but I am about to start designing a 4phase SR drive and I am tempted to use 5.99
In this situation I actually work closer to the way that you do, and I do not “practice what I preach.” But I certainly understand the use of net classes. My real example is like an elephant and the mosquito which is trying to bite through its skin.
I am sympathetic to the idea that it may often be better to not separate grounds when the disturbances are not so severe. I probably do it more than needed such as in my present home project.
I appreciate your interesting and amusing response!
I think you are pointing out the need for respecting voltage differentials in net classes. I think that a 2d voltage table may be needed for this? I use 5.99 and recommend it. I think it has some nice advantages but I have not noticed that it does a great job wrt voltage differentials for net classes.
I have heard this mentioned before (irc or discord or here) so this is good. I have been conceptualising embedded die so how I would do this with mentor or kicad is bugging me
Awesome. Being able to limit a stub for some SSR would be great .
Now I want v7 (ipc-2581, some form of component DB …)
From those articles. As high frequency current likes to travel through GND zone along the signal track separation about 2cm (noones land) between digital and analog part at PCB should be enough in most cases. Of course not always possible, but continuous GND is generally better then two separate GND zones. It is opinion from those articles (Keith Armstrong if remember well) and I rather believe in it.
I’m also on team “don’t separate ground planes” but I use net ties for things like current sensing / voltage sensing
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