Decoupling capacitor via placement

Hi everyone,

reading about the “proper way” of placing decoupling capacitors I found several resources [1] [2] stating that the IC’s VCC pin and the capacitor should be connected with separate vias (as close as possible to each other) to the power plane, instead of connecting the capacitor and the IC directly with a trace. This should help reducing the inductance of the IC’s VCC pin connection. From my understanding this is only the case, if the trace connecting to the via is shorter then the trace that would connect to the capacitor.
Now my problem is, that I am not sure, if one can simply place a via in the solder pad of a component. I managed to find some information about via-in-pad production but it seemed like a special technique and not the standard way. But at the same time I also could not find a way of specifying the clearance of a via to a pad of the same net. Kicad just allows me to drop the via directly in the pad, which makes me think that apparently placing a via in a pad should not result in a problem.

So now I am a little confused which way to go:

  1. Connect the capacitor with a trace to the VCC pin and ignore the resources above.
  2. Connect the capacitor and the VCC pin with separate vias to the power plane while running the risk of accidentality placing the vias to close or in a pad.
  3. Directly place the vias in the pads.

I am looking very forward for your advices, thanks a lot :slight_smile:

I am not sure your advice is correct. If the IC pin is directly connected to the plane by use of a via then the decoupling cap can not really do its job of protecting the rest of the circuit from the bad stuff comming from the IC.

So for this reason normally one connects the cap directly to the IC via a trace and then the cap to the plane by use of a via. The GND connection of both the IC and Cap are however done directly by use of a via to the ground plane (The cap should provide a buffer for the needed switching currents of the IC such that these do not come from the planes).


Thanks a lot for your answer!! :slight_smile:

One of the resources I linked states: "The idea of sequencing your bypass connections from the VCC plane, to a bypass capacitor, and then to you IC power pin is very old. Those who advocate this approach usually justify the circuit (if there is any explanation at all) as an attempt to construct a filter network with the stated objective of “keeping power supply noise contained at the IC site, preventing it from getting out onto the larger pcb”. " … and then they go on to explain why this is not correct :upside_down_face:

Do you mean by directly, that the via is / can be placed in the pad of the capacitor?

In my opinion main task of decoupling capacitors is to provide enough source for current pulses needed by IC to avoid voltage deeps disturbing its work. If you wont to protect rest of the circuit from what IC generates then you use ferrite bead between VCC plane and IC VCC.

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Texas instruments provides exvelent resources.
A search for decoupling capacitors will turn up invaluable professional advice.

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Do you only wont to make your job as good as possible (I always wont it) or you really have IC with so high dI/dt as were mentioned in resources you linked?

Till now I used only 2 layer PCBs (just to inform you that I have no practical experience).
There are PCBs with VCC and GND layers very close to each other and with special material between them increasing capacity. At such PCBs the PCB capacity is the source for the highest frequency components of IC current pulses so the VCC and GND pins should be connected as close as possible to planes. I think that suggestions you read may come (partially) from such designs.
I have read that in standard PCBs the capacitance between VCC and GND layers are too small to have important effect. So I would look mainly at connection length between capacitor and IC. And keep in mind that vias also have their length.
As I know (never used it) vias in pads have to be small enough (less then 0.3mm, better probably 0.2mm) to not stole the tin during soldering.
I have many times placed vias such that their copper just touches the capacitor pads (but I think of vias having 1mm copper diameter and 0.5mm via diameter). In my opinion the risk you write of placing too close via to pad is the question what is the tolerance PCB manufacturer drills the holes to avoid that via hole to stole the tin. So in another words to be sure that there is at least a thin line of solder mask between pad and via hole.
Conclusion: I suggest your option 1.

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“'Via in pad” is a special technique for high density designs. It’s a very small via which is capped so that the solder doesn’t flow into the hole. Very expensive. If you assemble and solder manually you can put normal vias in pads and the manufacturer won’t probably have any objections. But you have to know what you are doing. Solder paste goes into the normal 0.3…0.5mm via hole if soldering is automated and there’s no good connection between the pad and the component.

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I just want to make my job as good as possible, especially here since the proper placement does not increase the workload but could have major difference on the functionality. So I was curious what the best practice is.

Thanks a lot for that advice! I think that solved the issue for me. Placing the vias as you described results in really short traces. That way the connection described in the resources I linked above starts to makes more sense.

Also thanks a lot for the clarification that the via in pad problem definitely is no fabrication but only a solder issue! :slight_smile:

I think you’ve received some great advice here.

Remember the goal is to make the impedance between the bypass capacitor and the IC as small as possible. Since this impedance is most important at high frequencies, trace/lead inductance is especially worth avoiding. Therefore, the bypass cap gets placed as close as possible to the IC lead, and has vias placed as close as possible to this pad, connected to the power plane. In really sensitive/higher power designs you can even use multiple vias to reduce inductance.

So usually it’s [VIA]-[BYPASS PAD]-[IC].

I would also caution against putting vias too close to pads. In addition to tolerance from drilling, you also have to worry about the via stealing solder paste from the pad. This can be avoided to some degree by tenting the via, but now you have to worry about soldermask tolerance and drill tolerance to ensure the hole is really plugged. Easier just to move the via away from the pad slightly. 4mil or so is enough usually.

In what frequency range are your components working?
For the AVR microcontrollers I use (Upto 20MHz or so) I just slapped on some decoupling caps with relatively short wires and never had a problem with them (In this regard at least)
I have some experience with the “Blue Pill” boards from china, and though layout looks like barely adequate, and they have no decent GND plane they still “work”. I have not used it’s ADC yet. I’ve read on forums you can not get more then 9 or so noise free bits out of the ADC due to bad PCB layout, while with a better layout 11 clean bits should be possible.

The quality of decoupling gets more important if analog and digital is mixed, and also with higher frequency of the chips. Those GHz arm cores, DDR chips and FPGA’s are a whole different beast then some smallish uC.

“Info” from the internet is soo opinionated, and without hard data or real measurements (Just like this post) I’ve also read those opinions of connecting the caps directly to the pins, and place the via a bit further for “filtering” purposes, but don’t know what’s true of it.

Generally speaking lower impedance is better.
Shorter tracks have lower impedance.
Multiple tracks parallel also have lower impedance.

So for what I can get from your screenshot, I would both use 2 via’s and directly connect the capacitor to the uC pin.

For what I’ve read about Via-in-Pad, the trouble is with the cappilary action of the via which sucks away too much solder from the pad. Possible solutions are:

  • Don’t use them.
  • Use small via’s, so les solder is sucked in.
  • Have the via’s filled by your PCB Fab.
  • Expand the solder mask cutouts with the approximate volume of the via for those pads.
  • Use Wave soldering.

I have collected some links for decoupling (bypass) capacitor layout in Does the connected trace to VCC matter here?.

Another good reference is the " Printed Circuit Board Design Techniques for EMC Compliance: A Handbook for Designers" by Mark I. Montrose from the IEEE press. Chapters three and four give some practical advise on capacitor decoupling, trace layout and termination. Being from the IEEE press, it walks through the “why” if you want to underlying theory and real measurements.

I try to keep vias close to the pad and lead traces very short. Be aware that vias to the power plane may be lower impendace than a trace, as pointed out in the reference. Here’s one of my layouts for reference:

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Thanks a lot for pointing me to all this further information! It seems, that there is no right or wrong regarding the placement while different opinions exist… :crazy_face:

I will try to get my hand on this book but I could not find a free PDF of it online. Never the less they have the printed version in the library.

Frequency should not be a problem but I am using a digital isolators (ADuM1201) and in the AN-1109 application note for the board layout guidelines they deal in detail with the topic of EMI mitigation. That’s where I started to look into proper decoupling again.

I didn’t read that book but I suppose you can replace it with:

I think it is enough for most pcb designers.

This is a lot. Thank you for sharing this. I couldn’t find them online as well.

I can also share links for article series about EMC design not directly aimed at pcb design but don’t know if KiCad forum is right place to do that.


I see no harm! I’d enjoy reading it, it’s important material.

This is excellent @Piotr, I have not seen this before. It lists the Montrose book, @HaLed’s first link and IEEE transactions as references.

Regarding @HaLed original questions, Figure 1D and Part 5 of @Piotr’s references are a great place to start looking.

I would not say it this way. I would suggest it is like selecting the acceptable trace width given the required current for that trace. It just has a few more variables to understand. If I have an IC’s switching rise time (from it’s datasheet), operating frequency, power draw, number of power pins and size of the PCB, I can come up with a capacitor decoupling array strategy. Understanding the fundamentals shown in @Piotr’s references is the difference between using rule-of-thumb opinions and engineering a robust design solution.

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About 2004 I found an interesting serie of EMC articles by Keith Armstrong (for many years I didn’t know if Keith is a woman or men name). Later they became no accessible, but when I tried to find them few years ago I found them once more:

I wonder why previously my links were changed to rectangles (in source they were just lines) and now it looks my links are lines in source and in result. In both cases these are links to pdf-s.

And probably the same but modified:

Change 1 in ‘part_1’ in address to 2,3,4,5,6 to get the rest.

I found those time many, many pdfs googling for EMC, but these in my opinion are the best compendium of all EMC subjects.


The problem with current ICs is that even you use classic 74HC00 serie you can’t be sure if (to reduce production costs) they are not manufactured with smallest possible technology with the result that slopes are much faster than in the same circuit from the same manufacturer made decades ago.