reading about the “proper way” of placing decoupling capacitors I found several resources   stating that the IC’s VCC pin and the capacitor should be connected with separate vias (as close as possible to each other) to the power plane, instead of connecting the capacitor and the IC directly with a trace. This should help reducing the inductance of the IC’s VCC pin connection. From my understanding this is only the case, if the trace connecting to the via is shorter then the trace that would connect to the capacitor.
Now my problem is, that I am not sure, if one can simply place a via in the solder pad of a component. I managed to find some information about via-in-pad production but it seemed like a special technique and not the standard way. But at the same time I also could not find a way of specifying the clearance of a via to a pad of the same net. Kicad just allows me to drop the via directly in the pad, which makes me think that apparently placing a via in a pad should not result in a problem.
So now I am a little confused which way to go:
- Connect the capacitor with a trace to the VCC pin and ignore the resources above.
- Connect the capacitor and the VCC pin with separate vias to the power plane while running the risk of accidentality placing the vias to close or in a pad.
- Directly place the vias in the pads.
I am looking very forward for your advices, thanks a lot