Yea, there is basically one light matrix with about 100 LED lights connected, which causes the most connections, rest is buttons and endless encoders, and 3 potentiometer
I am designing all 2 layer boards with one layer 100% destined to GND to have continuous GND plane ensuring the best return current path for each current.
My example of such PCB:
For your PCB I would strongly reccomend switching to 4 layer PCB with both internal layers being GND or one GND and second VCC.
Hey Piotr.
This link is very helpful. Thank you so much.
I was planning to avoid using a 4-layer PCB, since that’s probably a whole other level I’d have to learn about, and I assume it’s also fairly expensive?
Looking at my layout, what would make you suggest going with 4 layers?
Or maybe the better question is: what fixes would you recommend as a minimum if I want to stick with 2 layers?
You’re basically saying that when using a 2-layer board, you don’t route anything on the back layer so you can keep it as a solid ground plane, is that right?
I guess you are right. It seems like a 4 layer is the safer option. Maybe more expensive, but probably worth it and no surprises, and at least there won’t be any surprises with ground.
I turned the board into a 4-layer PCB: the 2nd layer is for power, and the 3rd layer is for ground. I filled both layers across the entire board.
I can’t seem to solve one issue though. For some components, the pad color doesn’t change to the expected power or ground color, it just stays red (top layer), or when I check the bottom layer, it turns blue.
This only happens with certain components, and I’m not sure if it’s because I placed them on the backside of the PCB ( they’re flipped).
The “green arrow in the picture” shows how I would expect a ground pin to appear. The “red arrow” shows the issue I’m having on some components.
KiCad also still asks me to connect all the power and ground pins manually, but I thought that shouldn’t be necessary if I’ve filled one layer entirely with power and another with ground?
I am having the same issue with the power layer:
You need to spend some time in the Pad Properties to see what is available to Edit/Change. Double Left click or hover then Hotkey E on a pad and up will show the below:
THT pads are on all layers if Copper Layers is set to All (cyan arrow). Open the list available and select the layers you want the pads (watch the green symbol change).
If you want different pads on different layers, see the yellow box.
If you decide to change some individual pads, it is a good idea to tick only “Pads” (untick the rest) in the Selection Filter (magenta arrow) otherwise it can be difficult to select only a pad in a footprint.
If you want to change many/all pads in a footprint, this needs to be done in the Footprint Editor where you have the ability to “Push pad properties to other pads” (hotkey E on the pad in the Footprint Editor then see list).
Finally, take note that there are three pages of Pad Properties: General, Connections & Clearance Overrides.
Happy experimenting.
Hey jmk. Thank you very much for your help.
I checked that already and its set to all copper layer, the settings are identical to the one with the green arrow.
Edit: I figured it out. A simple restart fixed this issue. I have no idea why though 
Hi, my point was maybe not to leave the “All copper Layers” selected.
If you use, say, “Connected layers only”, you will find the below is shown:
The pads are now only on their connected layer. You will notice there is a fine red circle in the pad. This shows that the layer currently selected is the Front Layer. If I changer the layer to Back, all those red circles will change to blue, or Int2, will give orange circles but all the pads will remain their current color.
Oh I see. I was wondering about this.
Lets say I have GROUND selected, in theory pins like SDA or 3.3V PWR shouldn’t be orange. Does it cause issues if I design the board this way? Or is it mainly just for better visualisation? Also would I need to set Vias to “connected layers only” as well?
So basically I should set everything to connected Layers only?
With the GND planes on both sides, your PCB looks mostly OK-ish, because each footprint has a GND pin that stitches them together. But there are a few quite long sections of copper on the GND plane that are free floating, and that is not ideal. I recommend you add some extra stitching via’s to connect the GND plans together to remove those long sections that are only connected on one side. Something like in the screenshot below (I put some green dots as indications for via locations).
But for a keyboard design like this it’s not a huge issue, especially when the signal lines are slew-rate limited (And they should be).
Also, long rows of via’s are not ideal, as they create gaps in the GND planes. Avoid doing things like:
And you should also add a GND via close to where the signal changes the reference GND from the top layer to the bottom (or vise versa).
Also, long parallel tracks create a relatively strong coupling and thus also crosstalk between signal lines. A very simple way to reduce this is to change the signal order when changing layers. For example, if you number the red horizontal wires 1, 2, 3, 4, 5, 7, 8 from top to bottom, then use something like 1, 4, 7, 2, 5, 8, 3, 6 for the vertical blue tracks, and change the order to something different yet again when the tracks go to the front layer again. The idea is that a bit of coupling is harmless, but strong coupling can induce errors.
And last: Your via’s look very small, and this is a production issue. Thin drills break easily and thus have to be drilled slower. Often PCB manufacturers charge extra for very small (micro) via’s.
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Hey paulvdh.
Thank you so much for your help and recommendation. If I use a 4 layer pcb I should probably avoid most of those issues? I might still fix it for 2 layer pcb though. Not sure what’s best yet.
About the vias. I have a via diameter of 0.6mm and a via hole of 0.3mm. I thought that would be quite standard, or is that too small?
I had a quick peek at the recommendations of PCB way:
Your annular ring width is now (0.6-0.3)/2 = 0.15mm and that is the minimum specified at the PCBway website. I’d rather go with 0.2mm, so that would be an outer diameter of 0.7mm.
4-layer PCB’s are easier to design, but are also more expensive (especially for prototypes, for batches >100 the price difference is relatively smaller). Some PCB designers always use 4-layer PCB’s because they find their own time more valuable then the PCB cost. But this PCB is still very easy to do on two layers. I would stay with 2 layers, but it’s your project, your choice.
Thank you so much, really appreciate your help. I’ll change the diameter to 0.7 mm, shouldn`t be hopefully a big issue and I am more on the safer side
At my PCBs (like the example I show) all vias are GND vias. Whenever possible I use 0.9/0.5 via. If there is no room I use 0.8/0.4. When at the end of design I just randomly add some vias at big top and bottom GND areas I use 1/0.6.
This example is several years old PCB and there are probably even bigger vias.
Vias with 0.3mm hole I use only at ICs thermal pads.
My conservative approach come from 80s when it happened (here) that via could have no connection or could lost it in few months. The bigger hole the less chance of problems.
When recently I asked my contract manufacturer (very small company) if I could use 0.25mm hole in vias (at thermal pad of very small IC) the answer was “Better not do that.”
Designing 4 layer is much simpler than 2 layer.
With 2 layer I assume I need not to route GND so I hide GND connection lines when trying to find element positions that will allow me to route everything at top.
With 4 layer (I started to use it recently) I assume that except no problems with GND I will also use bottom layer for all supply connections (I use both inner layers for GND). Having no supply at top helps me a lot.
Whatever you will do you will have GND consisting of lot small areas. Giving a return current chance to go along signal current reduces PCB emissions and sensitivity. It was not important in 80s, but is very important nowadays. Even ICs with the same symbol as manufactured in 80s can now have 10 times shorter slopes (die shrinking reduces costs but also internal capacitances). And about sensitivity. Now each of us have very strong source of high frequency disturbance - try to put cell-phone just on your working pcb and call someone.
You can read more here:
Exactly. But the reason is to let return current travel just along signal track. Return currents (I’m not interested in DC) not travel the shorter way but they prefer to go just under track and allowing for it reduces the area surrounded by current and field emission (reception) is proportional to this area.
From the post just before Paul entered:
Copper layers is set as “All copper layers” Default for THT pads, but select whatever you wish.
If I was looking for as large as possible Ground Plane on an internal layer, I would not have unconnected pads on the Gnd. Plane internal layer. Same goes for Vias.
I’m not an EE, but a while back I did a fair amount of looking in to what ground routing was all about; you can find my notes and references here. It’s well worth following those references if you want to get into the details. (The longer summary there and shorter one here are my work; I welcome corrections to them if you have references (including my own). But there’s a lot of misinformation about this floating around, and apparently even many experienced EEs aren’t too up to speed on all of this.)
There are basically two situations you have to consider completely differently when it comes to dealing with ground on a PCB.
“DC” Ground
The first is “DC” connections or signals, those changing at well under 1 kHz. For these a device’s connection to be ground wants to have low resistance and be capable of carrying as much current the device is likely to sink on all of its inputs at once. Routing makes little difference except inasmuch as it increases the resistance of the connection back to ground, and you can usually compensate for this with wider traces. There are equations kicking around for determining the resistance of a trace of a given height, width and length; you can use these with Ohm’s law if you really want to get into this, remembering you need to analyse your power outputs/inputs, too.
AC Return Paths
For signals at 1 MHz and above, the return path is often not exactly what you’ve routed on the board (except for properly constructed balanced pairs) but instead will use whatever ground routes on the board are available that follow as closely as possible the signal path. (The signal itself is carried in the electrical field between the signal path and the return path; this is where EMI comes from.)
(And actually, the nominal frequency of the signal here is not really so much about how frequently you change from low to high or vice versa, but about the slope of the edges of those transitions: modern devices have much faster edges than old 1970s ones and thus have a much higher effective frequency for many analysis purposes, even if they are nominally both e.g. 1 MHz clocks. This has all sorts of implications that I won’t get into here.)
Generally, you want to try to make sure you’re providing some sort of path to ground as closely parallel as possible to each signal path. This could be done by actually putting a ground trace in parallel with each signal trace, as closely as possible to the signal trace. Often putting the return path on a different layer directly above or below the signal path will leave it closer than a parallel trace on the same layer.
This is why ground planes work so well: it’s a convenient way to ensure that there’s a return path parallel to every signal trace. But note that interruptions to the ground plane can break this. This is dramatically demonstrated in the following image with signal lines going straight across the board, but a large cut-out in the ground plane on the other side: you can see that the signal returns can’t follow the traces, instead having to go a long way around. This gives you a big gap between the signals and return paths, which is a big EMI field that can both interfere with other things and is much more subject to interference from other things, degrading the signal integrity.
Note that ground planes should not be confused with ground fill (many people do this): as you can see from the above a ground fill that’s heavily broken up is far from a ground plane and in many cases will provide essentially no help at all for signal integrity, or even degrade it.
The issue with interference in AC signals is when two separate signals share (usually just partially) a return path; this can cause interference between the two, almost as if the original signals were partially sharing their signal paths. You can see a perfect example of this above: the three signals all share a common ground return path around the cutout in the ground plane.
Whether a “star ground” does this depends on the actual signal paths; you cannot consider ground and signal paths separately. For any AC signal, its actual path is always the combination of the signal source and the ground return.
Your Ground Routing
In your case, it looks as if your board falls mostly into the “DC” category. (I assume you aren’t going to be pushing those switches at super-human speed.) So for those you need not care much about how the ground is routed; whatever you do to deal with the bounce inherent to the switches will be far more than you need to deal with any other signal integrity problems you might create.
I don’t see any LEDs, but if you are using any remember that PWM, depending on the speed, may be considered an “AC” signal to some degree.
The signals to the I/O expanders and the like are usually pretty low frequency, so I reckon you’re unlikely to experience issues there no matter what you do so long as you have decoupling caps as close to the Vcc and GND pins as possible.
The same goes for the signal cables back to the microcontroller. Normally if you were doing a ribbon cable connection for high-speed use you’d alternate signal and ground lines on the cable so that each signal has its own parallel return path. You might want to consider doing that, but at low speeds its often not necessary.
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This thread departed the KiCad station a long time ago . . . if it’s not come back anytime soon I’ll be cancelling it’s timetable 
If that doesn’t make sense then read this instead . . .
I don’t think it was ever a KiCad topic in the first place. I certainly can’t see anything KiCad-specific in it, not even in the head post.