I have only experience with 2 layer boards, and really only with SMD elements (I designed PCBs with TH elements so long ago that I had to design it using checkered card and pencil. Proper element placement is the biggest part of PCB design. Making traces as short as possible is the first step on the road. Placing resistors together and capacitors together is in my opinion absolutely senseless. I always try to be sure that I know which way each connection will go during routing.
With PCBs I route (one microcontroller + several elements around it) my strategy is:
- all bottom to be used for GND. No other tracks there. In most PCBs I reach that goal. Sometimes I allow myself for one ot two very short signal tracks at bottom,
- so I can hide GND connection lines during placement as I have GND everywhere one via from me. With KiCad 5.1.x to hide GND I delete it (text editor) from netlist (100% deletion) or place GND zone at top (close to 100% deletion - you have to press ‘b’ many times). With KiCad 6… as I have read it will be possible with no tricks,
- define power supply that way thet I get VCC made near one microcontroller corner,
- go with VCC under microcontroller (under but on top layer) and go out through all three rest corners and through its VCC pins (I use uC that have VCC at each side), that helps to reach with VCC elements around uC with no blocking (too much) other connections to uC pins. If you go with VCC around uC to connect it to all its VCC pins than you can’t connect anything to uC without jumping to bottom PCB side.
- as uC pins can be flexible used for many tasks at that stage I select right pin for each task to untangle the connections as much as possible,
- when I finish placement I in most cases know which way each track will go (I sometimes route some connections partially only to get the connection line out of the region I am interested to not disturb me in imagining which way the connections I am thinking about I plan to route.
But my PCBs are rather simple. I suppose that when someone has for example BGA (or many BGAs) it is not possible to imagine all connections during placement. But as he have not only 2 layers he has bigger possibilities.
There are many, many other considerations and sometimes the goals contradict each other.
The links I have given some time ago explain (among others) why I use all bottom for GND:
Few posts later in that thread I gave more links.
After reading all that you will understand most PCB design problems I think.
As I understand you are a programic/informatic man (if I were better in English I would probably wrote it differently) I associated it with one problem we had recently with software developers (in other firm).
I write it just because it is (in my opinion) a good example of how the software and hardware worlds differ. They just did something we had never expected anyone can be so thoughtless to do it that way. Imagine an array of 32000 data records (cards in access control system) stored in flash memory. Our program assumes that record filled with FFs or 00s not contains valid card so is skipped when searching for card. So if you need to delete one record you just program it to 00-s - one programming operation for one page (page need not to be erased first).
But someone there decided that in such situation (someone fired or lost his card) it will look better to not have empty records so we got a serie of orders to write 0s into n+1 record (erase it) and then program the right data into n record. To protect flash our program checks if it is possible to write data without erasing the page but as that record was just programmed to 0s it was never possible so each write needed to erase page first. He went through all array even only 5 records were not FFs. You can assume flash runs out by number of erase operations. So instead of 0 erase operations we got 32000 page erase operations. He should left that 00-ed record between others, but even not he could use the order ‘write FFs into records from 6 till 32000’ - it would not run out flash so much. By this solution he shortened the expected device live many times.