I am designing a 4 layer PCB which is stacked as Signal-GND-Power-Signal.
The power plane needed is smaller than the ground plane, do I need to add some ground copper pours so that the 2 middle planes can be of similar size? Does this operation help reduce EMI?
mid layer 2 (2) - power plane + grounded copper pour
Front-layer ICs are very sensitive to EMI and operate from 10kHz to 10MHz.
The bottom layer mainly contains switching regulators and related components.
I’m not an expert. I have never designed 4 layer PCB.
I have read that if you have the same copper pours at adjacent layers you form a kind of waveguide with open ends that allows for standing wave what is not good. If remember well it was written about regular rectangles what is not a case here. There were written that at one layer copper pour should be smaller.
I probably read it in one of articles I have linked here:
A lot depends upon the details of what you are doing, and added ground plane is not a bad idea. But examine the “layer stack up” of a standard 4 layer pcb. In the more common layer stackups, you will see that the top and bottom dielectric layers are thin (separating top copper from L2 and bottom copper from L3) while the middle dielectric layer is substantially thicker. This close spacing improves the tendency of the ground plane to conduct virtual image currents (caused by magnetic fields) which help to reduce EMI and stray coupling. So if your signals are on top copper, then L2 ground will give you much better shielding than L3 ground will. But an L3 ground will work better for signals on the bottom copper.
I have seen where 4 layer boards give you much cleaner waveforms in a boost converter (for example) than what you can get with a 2 layer board. These days, many eval boards from semiconductor manufacturers are routinely done with 4 layers. I used 4 layers for one of my most recent home projects, but that was for smaller size rather than performance. Four layers were not expensive with small boards (length = 100 mm) made in China.
The main function of the PCB is capacitance measurement. The core IC is TI FDC2214, which is a capacitance measurement chip based on LC resonance. There are also 4 high-speed op amps that provide active shielding for capacitive sensing. Both types of ICs are located on the front layers and they are sensitive to EMI and parasitic issue.
The bottom two ICs are a buck switching regulator (TPS62172) and a buck-boost split rail converter (TPS65133). Both chips require inductors, which can be a noise source for the system (not sure).
front signal
mid 1 ground plane
mid 2 power plane + ground plane
These are the layout examples given in the FDC2214 datasheet. I’m actually just trying to mimic their middle layer design, but don’t know if this is correct for my design since the bottom layer of the layout instance is very different from mine.
Is there any problem with having both power plane and ground plane on the same layer?
In general, there’s no problem. Of course it doesn’t make sense for all designs, some need for example a full power plane across the whole board, some need multiple different power planes with different voltages. But your design seems fine and the different bottom layer probably doesn’t matter much.
If signal at bottom crosses the gap between VCC and GND at L3 than probably having no GND there but whole L3 being a VCC can be better. VCC can also work well as return path.
Is there any reason you not want the power plane to stretch over the whole layer as the GND plane does? usually this will give the best EMI because you add some (small) capacitance from the board itself.
One reason is because there is a voltage regulator (TPS65133) in the lower half of the bottom layer that is not powered by the voltage of the power plane, and it will output ±5V.
Another reason is that the layout example in the datasheet of the top layer chip (FDC2214) does not use full board coverage power plane, so I just try to mimic the layout in the datasheet, although I don’t quite understand why.
Once upon a time I was responsible for designing electronics for Hospital/X-ray - a terribly EMI-Noisy environment and products needed UL certification. I was compelled to learn and teach company classes on this…
Beyond ‘Lab’ testing, the best (because it was clearly written with examples) resource was this book,
“EMC For Product Designers” by Tim Williams. (mostly geared toward compliance to European Standards).
My book is 1995 - Here’s a link to newer book (2016) Chapter 12, see the Contents/Index, if curious…
It has chapter on PCB design with Ground-Plane design. I imagine there’s plenty of good info on the internet…
ADDED: I re-visited the Book (the Geek, in me)… You may get all the info you need from the internet. I like Books and Paper I can hold. Though my book is 27yrs old, it contains very useful info and these screenshots suggest a world of discovery re PCB (for the curious)… You asked about Ground Plane on Internal Layers (referred to as ‘Embedded Stripline’)
