I subject my boards to a d^2y/dt^2 vector of 9.81 m/s^2 out the window when percussive maintenance has failed to make them work. 
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I like that acceleration and percussive maintenance. An unlucky person outside your window might feel board. 
He does explain later that the return plane can be of any voltage, I am by no means a technical expert, but I have hear that before, here an article from Altium a CAE Software company .
Ah hah!
and does this defenestration improve their usability?
It makes them reliably non-working instead of sporadically working.
In The Soul of a New Machine there’s an episode where junior engineers are getting nowhere with an erratic board. The senior engineer comes in, picks up the card cage and thumps it on the bench. Now it was deterministically non-working and the juniors could work out why. That’s experience for you.
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You are thinking DC. DC return current is out of interest in many cases. RF return current always prefer the closer plane to track (the same as it returns not the shortest way but following the track shape. I can’t proof why. I just remember it from many EMC articles I was studying around 2002-2004.
So for that current the problem is how it reaches the plane it wants to travel on. Because of this in high frequency designs it is mandatory to place capacitor between VCC and GND near any via on the fast signal track jumping from top to bottom as the return current in that place needs to change the plane. If there is no that capacitor the return current finds its longest way to jump from one plane to the other what make EMC emission and EMC sensitivity higher.
20 years passed. I don’t remember those things in detail. My knowledge really comes only from articles I mentioned here:
and here:
Hi thanks for the reply. No no high speed signal. Thanks for the suggestion in fact it is what I did in my pcb for this in the first level I tried to use it for the signals, The second and the third I left it “empty” and I made a large Copper pour or “power polygon” "(the second of mass and the third to 12v). Finally the last layer I used it to connect the things that I could not connect in the first layer.
In addition to this I have modified the pcb a bit so as not to use the tracks to connect the outputs but small polygons so I increase the current that flows. In addition to this I was told to improve the thermal masses for the 0805 pads that are on the output as being unequal they can get damaged.
Thank you all for the answers 
In summary, I received these feedbacks:
-Use the first and last layer mainly for signals while the two central levels use them to make power planes (second ground level and third power)
-Improve the thermal part of the pcb (I have no idea how to do it but to use vias but I don’t know where to put them).
-I have unequal thermal pads and for 0805 components (at the output) this can be a damage factor
-Using the polygons and then connecting the tracks, in this way there is more current passage area
These are several feedbacks I have received. Now my biggest problem is the thermal part … I state that the first 3 ic (starting from the right) will absorb at the maximum for each track about 7A (in reality they will circulate about 5A but better to have a slightly more extended operating range) .
What should I do to improve the thermal part?
Your PCB is a different beast so, this is just FYI
I designed some Stepper-Motor control boards and put a Pour (Net=GND) on Top Cu layer underneath the Chip to absorb and transfer heat away.
I also did a FEA thermal analysis (I’ve posted FEA info on this Forum, if interested). And, geeking around, I designed a Thermal Camera to inspect the running system (one thing leads to another )
Screenshot (look at the ‘T’ shaped pour…
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Thanks, Piotr.
I think you are probably correct. The close proximity and high dI/dt would cause magnetic coupling so that current would flow through the plane as close as possible to the track but in the opposite direction. With no DC current flow through the plane, the current would need to circulate back through a longer path. Still I wonder if a ground may be somewhat better as DC and AC are flowing closer to the same path.
I always use
top:signal/power;
inner1:ground;
inner2:ground;
bottom:signal/power
the current return path for signals will almost always be in the adjacent layer. above 30-100kHz the return path for current is the path of least inductance, below that in the path of least resistance. If you use
Signal
Ground
Power
Signal+ground fill
watch out for the return current in the power plane crossing slots. Meaning, don’t lay out a trace on the bottom which crosses a slot in the adjacent (power) layer. it is very easy to do and I see it a lot.
Also the impedance of decoupling caps will differ depending on if the cap is placed on the top or bottom layer.
With multilayer (6+) boards, you will get good capacitance between the power and ground planes if they are placed adjacent to each other. due to space between inner1 and inner2 in most 4-layer stackups, you will not get the same benefit, in my experience it is usually better to lay power as traces on the top and bottom. I have done this stackup with many, many, boards over the years, including boards which required FCC Class B certification, and it has worked well for me.
I recommend Bruce Archambeault’s book, “PCB Design for Real-World EMI Control”. Also, the 2nd ed of Henry Ott’s book I recommend if you are serious or even semi-serious about designing PCBs you familiarize yourself with signal integrity and EMC. The basic concepts are very simple.
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This sounds good, but I think that the requirements of the design must come into consideration. In ancient times, many products worked OK with 1 sided or 2 sided boards. My recent 4 layer design has one ground plane and parts on both top and bottom. With the possible exception of a boost switching voltage regulator, there is not much very critical in the layout. I was interested in fitting the board into a modest size pill bottle (really) and also within the 100 mm limit for lowest price from JLCPCB. The board works OK. I suppose that if you are routing GHz signals or 8K video, then my layer assignments might not be good enough. But I was not doing that.
In your case, shouldn’t it be coffee shaped?
The T shaped area which @BlackCoffee described is one good thing to do if I correctly understand what you are trying to do.
Do your ICs have belly pads which connect to ground? If they do…the belly pad should be soldered to ground copper zone on the top layer. Then, via stitching to the ground layer should be done close to these ICs. Subjectively…these techniques work better than I expected.
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Very good idea. I will always consider it. Till now thinking about 4 layer PCB I assumed signal-GND-Power-signal stack up but never designed 4 layer.
Now with my first 4 layer PCB I have to use different stack up.
Previous revision of my PCB was 2 layer with shield box on top connected with many vias to bottom being 100% GND. So all signals really in shielded compartment (each line coming in/out filtered at shield border). I could do it 2 layer as I had microcontroller without thermal pad and I could go under it with VCC and spread it radiantly to other elements. Next revision will have QFN microcontroller. So I think of following stack up:
top: signal/power
inner1: ground
inner2: power
bottom: ground
Bottom has to be ground to screen everything (including power) in the compartment formed by shielding box connected with ground plane at bottom.
I hope I will be able to have all signals at top as in other case their vias will be ‘visible’ on a border of my shielding (holes in bottom layer). To not get into additional costs I assume only standard vias.
Hi the Ics (of “power” have a pad but where the positive (12v) must be connected. So I think I will fill it with via in order to connect to the power layer. I thought of using layers 1 and 4 for signal then the second power layer (12v so I can connect via the first layer) and finally the third layer a ground plane How should I “protect” the smd 0805 components that are above the connector (J1)?
When you say above, is that with respect to orientation of the image? I question because I see no space on the top layer above the connector. But generally it is good to have the ground plane as close as possible to the signal layer. And I assume that your signal layer will have these 0805 components mounted and connected with tracks. (??)
Hello sorry, I expressed myself badly. The components below J1 are all 0805 components. These components are grounded on one side and connected to the output of each IC on the other. I thought of creating a small polygon for each 0805 in order to connect to the second layer (gnd plane). That way I shouldn’t have any major problems
In theory, it seems possible that if these numerous 0805s were to share ground vias, the via impedance could cause coupling between the 0805 ground ends. But I would probably do that, if the layout permits. I would use one topside ground zone spanning across the multiple 0805s, and connecting down to the second (ground) layer with multiple vias. Or if some other tracks would break up a single top layer ground zone, you could use a few zones, each with multiple vias. What do my comrades on this forum think?
Once in my life my board was screwed up by a via which failed to connect due to poor fabrication. Ever since then, I try to use redundant vias everywhere, at least on my own boards.
I improved my pcb in this way:
- Using polygons for output this way I have more surface
- Divisions of the 4 layers in this way: 1layer signal + ground plane, 2 ground plane layer, 3 power plane layer while the 4 signal + 3.3v plane.
- To improve the thermal part of the ic I put a couple of ways through the board
- In order to distribute the current in the best possible way, I made some routes that connect to the power level.
- Also on the input of the 12v I made a layer on the F MASK level so I have the copper uncovered and it is better.
Other things to improve I do not see them. I leave you a couple of screenshots below.
Thank you all
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