Hi everyone i am creating a small 4 layer pcb with kicad. The purpose of this pcb is to control and monitor the lights of a car (not for road use) and without having to resort to old relays and fuses I have opted for high Infineon switches as they have all the safety features I need. Everything is controlled by a wroom esp32 s3 via mqtt. As the power Ic of the esp I used a MAX16904 with 3.3 and 600 mA output. My question is related to power / ground plans. Since I have 4 levels of pcb, I thought of creating 3 power supply plans (12v) top, in1 and in2 all crossed by via (via stitching) in order to reduce the current and the heat produced. While the last level (bottom) creates a gnd plan. Under the ic power supply I made a ground plane that crosses all 4 levels thanks to the vias. I attach photos of the pcb (I donât have the contour lines yet because I still lack a couple of components related to the logic part) ⌠I also tried to divide the circuit into two parts: the upper part is related to Power while the lower part on the logic I hope I was clear enough 
I leave you the screenshots below.
Thanks everyone for your time
Iâm by no means an expert here, but for a four layer board most of what Iâve read is that you put a single power plane on layer two, ground plane next to it on layer 3, then you have layers 1 and 4 for your logic and routing of signals and such.
In terms of power, it looks to me like youâve sized them up for certain pins quite nicely, but it would help to see the schematic youâre using, and to have some idea of the power draw youâre expecting. But if you are infineon modules (or any type of modules) maybe itâs better to only run the control signals on the board, and to use a wiring harness to do all your power connections?
Just a thoughtâŚ
A ground plane filling one inner layer is usually a good start.
I rarely bother with power planes.
Beware of power tracks on inner layers as the current rating is lower than on the outside
I do not know whether you have any hi slew rate current signals in your board.
With the usual 4 layer stack-up, you have a thin dielectric between each outer two layers and the next layer towards the center (so 1-2 and 4-3). The spacing between layers 2 and 3 is typically larger. The convention is to put most of your signals on the top layer, and have layer 2 be a ground plane.
The benefit of this is that close proximity of the ground plane to high di/dt signals will provide relatively good shielding of magnetic coupling between adjacent traces for example. You will also end up with less stray inductance. If your signal,ground layer arrangement is not 1,2 or 4,3 you will lose those shielding advantages. I guess you could use an inner layer as your main signal layer but this would greatly increase the number of vias required so does not make obvious sense.
I suppose that if the board does not have high dI/dt signals then this will all not matter so much, but in my opinion if you are spending for a 4 layer board, you might as well use it in the best manner.
I just saw this video with Eric Bogatin about the topic, very interesting, albeit a bit long, still very recommendable
I started this video and the guys sound knowledgeable. ButâŚ
About 13 minutes in, the bearded guy says that this arrangement is pretty good, because return current for the bottom signal layer return on the power plane. I have some doubts about thisâŚ
But lets say that I have current flowing from a charged capacitor on one end of the board through a trace to a transistor to ground on the other end of the board. Any return current will flow through ground and not through the power plane, even if you have only one solid power plane. In other words, in my opinion, the power plane might not work as a return path to minimize crosstalk and ground bounce.
I subject my boards to a d^2y/dt^2 vector of 9.81 m/s^2 out the window when percussive maintenance has failed to make them work. 
I like that acceleration and percussive maintenance. An unlucky person outside your window might feel board. 
He does explain later that the return plane can be of any voltage, I am by no means a technical expert, but I have hear that before, here an article from Altium a CAE Software company .
Ah hah!
and does this defenestration improve their usability?
It makes them reliably non-working instead of sporadically working.
In The Soul of a New Machine thereâs an episode where junior engineers are getting nowhere with an erratic board. The senior engineer comes in, picks up the card cage and thumps it on the bench. Now it was deterministically non-working and the juniors could work out why. Thatâs experience for you.
You are thinking DC. DC return current is out of interest in many cases. RF return current always prefer the closer plane to track (the same as it returns not the shortest way but following the track shape. I canât proof why. I just remember it from many EMC articles I was studying around 2002-2004.
So for that current the problem is how it reaches the plane it wants to travel on. Because of this in high frequency designs it is mandatory to place capacitor between VCC and GND near any via on the fast signal track jumping from top to bottom as the return current in that place needs to change the plane. If there is no that capacitor the return current finds its longest way to jump from one plane to the other what make EMC emission and EMC sensitivity higher.
20 years passed. I donât remember those things in detail. My knowledge really comes only from articles I mentioned here:
and here:
Hi thanks for the reply. No no high speed signal. Thanks for the suggestion in fact it is what I did in my pcb for this in the first level I tried to use it for the signals, The second and the third I left it âemptyâ and I made a large Copper pour or âpower polygonâ "(the second of mass and the third to 12v). Finally the last layer I used it to connect the things that I could not connect in the first layer.
In addition to this I have modified the pcb a bit so as not to use the tracks to connect the outputs but small polygons so I increase the current that flows. In addition to this I was told to improve the thermal masses for the 0805 pads that are on the output as being unequal they can get damaged.
Thank you all for the answers 
In summary, I received these feedbacks:
-Use the first and last layer mainly for signals while the two central levels use them to make power planes (second ground level and third power)
-Improve the thermal part of the pcb (I have no idea how to do it but to use vias but I donât know where to put them).
-I have unequal thermal pads and for 0805 components (at the output) this can be a damage factor
-Using the polygons and then connecting the tracks, in this way there is more current passage area
These are several feedbacks I have received. Now my biggest problem is the thermal part ⌠I state that the first 3 ic ââ(starting from the right) will absorb at the maximum for each track about 7A (in reality they will circulate about 5A but better to have a slightly more extended operating range) .
What should I do to improve the thermal part?
Your PCB is a different beast so, this is just FYI
I designed some Stepper-Motor control boards and put a Pour (Net=GND) on Top Cu layer underneath the Chip to absorb and transfer heat away.
I also did a FEA thermal analysis (Iâve posted FEA info on this Forum, if interested). And, geeking around, I designed a Thermal Camera to inspect the running system (one thing leads to another )
Screenshot (look at the âTâ shaped pourâŚ
Thanks, Piotr.
I think you are probably correct. The close proximity and high dI/dt would cause magnetic coupling so that current would flow through the plane as close as possible to the track but in the opposite direction. With no DC current flow through the plane, the current would need to circulate back through a longer path. Still I wonder if a ground may be somewhat better as DC and AC are flowing closer to the same path.
I always use
top:signal/power;
inner1:ground;
inner2:ground;
bottom:signal/power
the current return path for signals will almost always be in the adjacent layer. above 30-100kHz the return path for current is the path of least inductance, below that in the path of least resistance. If you use
Signal
Ground
Power
Signal+ground fill
watch out for the return current in the power plane crossing slots. Meaning, donât lay out a trace on the bottom which crosses a slot in the adjacent (power) layer. it is very easy to do and I see it a lot.
Also the impedance of decoupling caps will differ depending on if the cap is placed on the top or bottom layer.
With multilayer (6+) boards, you will get good capacitance between the power and ground planes if they are placed adjacent to each other. due to space between inner1 and inner2 in most 4-layer stackups, you will not get the same benefit, in my experience it is usually better to lay power as traces on the top and bottom. I have done this stackup with many, many, boards over the years, including boards which required FCC Class B certification, and it has worked well for me.
I recommend Bruce Archambeaultâs book, âPCB Design for Real-World EMI Controlâ. Also, the 2nd ed of Henry Ottâs book I recommend if you are serious or even semi-serious about designing PCBs you familiarize yourself with signal integrity and EMC. The basic concepts are very simple.
This sounds good, but I think that the requirements of the design must come into consideration. In ancient times, many products worked OK with 1 sided or 2 sided boards. My recent 4 layer design has one ground plane and parts on both top and bottom. With the possible exception of a boost switching voltage regulator, there is not much very critical in the layout. I was interested in fitting the board into a modest size pill bottle (really) and also within the 100 mm limit for lowest price from JLCPCB. The board works OK. I suppose that if you are routing GHz signals or 8K video, then my layer assignments might not be good enough. But I was not doing that.
In your case, shouldnât it be coffee shaped?
The T shaped area which @BlackCoffee described is one good thing to do if I correctly understand what you are trying to do.
Do your ICs have belly pads which connect to ground? If they doâŚthe belly pad should be soldered to ground copper zone on the top layer. Then, via stitching to the ground layer should be done close to these ICs. SubjectivelyâŚthese techniques work better than I expected.