Your PCB has (at least) three antenna’s on it (which is relatively long pieces of copper only connected on one side)
You could use via stitching, but just having a single good GND plane is good enough and you can just completely remove the copper pour from the top side of the PCB.
About those fuses, I think you know what fuses are for.
What is your intention with J3 and J4? It looks like these connectors have some signals but neither power nor GND.
If I understand well you concentrated yourself at not important parameter. If you have continuous GND at bottom don’t worry about GND fill at top. It can be divided in many isolated pieces - no problem. Each piece you connect with bottom GND with several vias. At ends and borders are enough. If area bigger then I also add some inside.
Here you can see my example:
Simply depends on what you want to do. A copper plane adds stability and (minor) protection against ESD (ESD events will likely contact the ground plane instead of signal traces). Two planes with vias in between will also conduct heat better than a single plane.
But in the end, probably doesn’t matter for such a simple design. Copper and vias are usually free, so no problem to add them. It will also work without them. But these antennas are bad, yes.
Piotr, paulvdh, thank you so much. So it sounds like I should just place things and route all the traces that aren’t ground, without worrying about isolated planes on the front, and then connect them to a solid backplane with vias?
And also, I should avoid long power runs?
As for the J elements, paulvdh:
J1 is obviously my Pi GPOI breakout
J2 and J3 are for I/O ribbon cables to peripheral sensors
J4 is for my ADS breakout board
J5 is a separate power ribbon to support J2 and J3
I considered combining power and I/O for J2 and J3, but JST8’s were difficult to manage on perf boards, so I went with JST5’s for I/O and a JST3 for power. I am rethinking that now, however.
Yes, a single good GND plane is the first thing to aim for. Your circuit (especially something as simple as this) will still work without it, but it will perform a lot worse in the EMC department
Nope, the length of the power tracks does not matter much You do want fairly wide tracks to reduce the voltage drop because of track resistance. Placing proper decoupling capacitors at the “end” of such tracks (or better, near IC’s) is important though. but for this board I assume the AMS1115 PCB already has the decoupling capacitors onboard. (You should not assume, but verify).
I believe those JST connectors have a bit of a different pitch, which is troublesome for breadboards, but if you design the PCB yourself, that is not relevant anymore. You can go different roads from there. You can try to make something universal, so it does not matter on which “channel” you put a sensor. Examples are the “UEXT” from Olimex and the “Grove” from SeeedStudio. Or you can go the other way and design your project on purpose in such a way that connectors can not be put in the wrong socked accidentally. (for example by using different pin counts). Having both power and signals on the same connector is an advantage either way. It reduces cabling, and improves signal integrity and reduces EMI.
Also, very likely you can put your SMT resistors under the ADS1115 PCB. Just because there is a breakout board on top of your PCB does not mean you can’t use that area for other footprints.
This is quite enough for a starter projects. Once your PCB’s become more complicated (and have faster signals) demands on the PCB also become a bit more complex. Over time you should educate yourself about signal integrity and EMC and how that translates to PCB design.
If you want to learn more read pdfs I linked here some time ago:
and
Those power tracks were questioned because they cut your GND and not because they were long.
Wow, this has been very educational. I think I may be about ready to submit it.
I did look at the ADS1115 breakout board and it takes care of decoupling. As for J3 and J4, I think I’ll just make sure and decouple on the peripheral end. I’ve got .1uF caps on the TMP36’s. For this small a project would I need a 10uF at the front as well?
I did have another question on basic design. I drew the J3 and J4 power traces like the upper example because I wasn’t sure and I had the room. But is the lower example also acceptable?
This far in this thread I find it incomprehensible that you do this:
Which makes me doubt what your interpretation is of:
I’ve been thinking about this for about 5 minutes and the only conclusion I can think of is that you did not understand half of what was written in this thread and I don’t know what else to add. Maybe re-read this thread?
Good to see you got rid of the top layer GND fill! Just adds lots of capacitance.
One more remark:
You have almost all signal traces clustered as close together as possible. Unless they are impedance controlled (which they are not), I find this a bad idea:
In parallel traces, signals always couple into the neighbor track. In most cases (including yours), this is not critical: Slew rates are slow, signals are uncritical or tracks are short. But as you asked for advice, here it is.
I learned this the hard way, designed a data acquisition board where a data line from an A/D converter was routed along a digital control line. Sporadically, glitches would occur… mystically depending on the analog input voltage (wtf?!). Cost me lots of nerves and two weeks of debugging.
So my advice is: Unless you are space constrained (or want to explicitly combine differential signals), after completing the board separate the traces so they are more than the minimum track-track distance apart. It does not need much, three track widths is already much better.
Also it reduces the probability of a short due to a dust spec in lithography.
Again, no big deal with this design. But I’d recommend making a habit out of it - just consider it as an additional post processing step before gerber generation.
yup… soo many designs are ruined because of this (I just reviewed a card with about 40 parallel traces with about 5th between them… 3 spare signal layers in the same area as well…)
Simple rule of thumb is the track separation should be 3h where h is the HEIGHT of the trace to its reference plane (in this case how thick is your CORE). If you were to put this as the clearance in the design constraints the tool will help you keep the traces far enough apart
With a 1.6 mm two layer board this would give some 4.5 mm separation…
I guess this rule makes more sense for 6-layer and up, where the prepregs or cores are much thinner.
Anyway one should not do high speed stuff on two layer boards (for pros, EMC tests pretty much ensure that).
For me the lower example is better as it at once makes a break in bottom GND shorter.
If you go with these tracks under R1,R2,R3 then a break in GND will be even shorter.
You can be right for multi-layer boards, but at two layer 1.6mm board top GND can give return path in 0.2mm distance from track and not in 1.6mm distance making signal loop area few times smaller.
Also:
In some rare cases additional capacitance is undesirable. For example at operational amplifier output can lead to instability. You should identify such cases when filling GND at top.
Sometimes I left between traces enough space to be filled by top layer GND and I find place to via its ends to bottom GND (extra track connecting two GND vias). You can find 2 such constructions in PCB I linked in post 10 in this thread (first vias North-West of microcontroller and first vias South of it).
Thanks paulvdh. I guess it wasn’t completely clear with all the changes. So is the problem the length of the power traces on the ground plane, and I should just duck them under only where needed? Or is the problem even running the power leads on the ground plane, and I should keep them on top and duck the signal traces?
I’m not going to repeat it again.
You are not running power on the ground plane. You break ground plane to run power tracks.
We are just trying to teach you the best practices. Even if it is not too important in case of this PCB.
The problem is having a break in the ground plane. The best would be to have whole bottom layer as GND fill and no other tracks there. I think it should be possible to reach that goal in that PCB case.
If it is not possible than breaks in GND should be as short as possible. I, personally, prefer to use 0R instead breaking GND but this can be considered an exaggeration.
The main drawback of 2L boards is not the missing ground plane. For SMT stuff, just flooding the bottom, routing 90% on top and hopping crossovers to bottom works well enough mostly.
The problem is that there is just no way achieving the equivalent of a proper, low impedance supply plane. Filling the top with VCC does not help on a board like this. Placing power polygons on the GND plane really would mess it up.
There’s more to say in terms of ground plane interruptions and signal integrity, but I guess that’s beyond the point here.
That’s a quite bad example, with hardly any effort to
I mean, 4 long dogbones all jumping over the same track…
It’s obviously just quickly thrown together, but it will work, especially for hobby stuff and when EMC compliance is not such a big issue. There always is some compromise between speed and effort.
It’s just not a good example.
I’m seeing $8 US for 5 pieces, 100mm x 100mm board right now from our favorite low end provider.
