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Tube amp schematic to pcb
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9
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164
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June 9, 2025
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Export multiple nets to STEP model
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0
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73
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June 9, 2025
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Filled zone & Layers
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44
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260
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June 9, 2025
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Assign an automatic track width to a net class?
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2
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98
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June 8, 2025
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Add ISA edge connectors to existing project
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9
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237
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June 8, 2025
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3D models removed from one KiCAD version to the next
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2
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189
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June 7, 2025
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ConfirmaXL IC design system with Kicad schematic capture front end
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4
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658
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June 7, 2025
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Mounting hole pad edge cut clearance?
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15
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355
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June 7, 2025
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Is there some wishlist for future KiCad library components?
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2
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168
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June 7, 2025
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Where are the default settings for Copper Zone Properties
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2
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232
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June 7, 2025
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Relay Contact & E-Stop mushroom PB
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2
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152
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June 7, 2025
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How to edit Pins
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4
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113
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June 6, 2025
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Network Port numbers used by KiCad Application
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4
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146
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June 6, 2025
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DRC Edge.Cuts Problem KiCad9
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11
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229
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June 6, 2025
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Pads on int1/int2 layer
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3
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112
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June 6, 2025
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Glitch/bug in footprint editor (pad attributes)
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4
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209
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June 6, 2025
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Kicad 9, can't open a schematic to copy something from it
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2
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114
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June 6, 2025
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How can I connect the MCU pad in F.Cu with a capacitor pad in B.Cu?
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11
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158
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June 6, 2025
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Panelizing multiple boards for JLCPCB
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21
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591
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June 6, 2025
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Cursor hover selects whichever window its over top
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2
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122
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June 6, 2025
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Does SKiDL work with AI?
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8
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249
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June 6, 2025
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Same-page net with same wire label not connected
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13
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259
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June 5, 2025
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Silkscreen layer keepouts?
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8
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127
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June 5, 2025
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Tuned value for vpulse parameters
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0
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77
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June 5, 2025
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Footprint in footprint editor not shown
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2
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86
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June 5, 2025
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Disagreement between NGSpice and LTSpice for ADA4522 opamp circuit
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12
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820
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June 5, 2025
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Design rules for hand-solderable layout
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3
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133
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June 5, 2025
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Are kicad 9 nightlies currently tied to stable release?
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4
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294
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June 5, 2025
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Enforcing nonzero skew between traces with custom design rule
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2
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139
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June 5, 2025
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Extra ratsnests wires on the PC board (Solved)
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10
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151
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June 5, 2025
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