I have to create a net tie on an inner ground layer for a 4 layer battery management PCB. However, I have not figured out how to do this. In the latest forum entry talking about net ties on inner layers it is mentioned that pads on inner layers will be possible starting with version 7. I’m on KiCad 9 and can’t figure out how to create a net tie footprint on an inner layer. Am I missing something or does someone have a workaround that passes DRC and is not super hacky like some previous suggestions I found looking into this issue (editing the text file manually and changing the pad layer)
I think that pads/netties on inner layers are not possible (atm); i’ve seen on the forum some requests to introduce them for some very special pcb constructions but i don’t know if the request has reached the proper place (github).
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Thanks for the reply. In my case it’s not even a special use case. The Texas Instruments reference board actually suggests doing it this way. I need to connect power ground with analog ground directly under the IC, but there is very little space around the tiny charger IC. The net tie should sit right under the ground center pad of the IC. There really is no other elegant way to do this. Either I would have to move some decoupling caps to make room for the net tie, which is undesirable, or I would have to stop using KiCad.
Ah ok, well thanks for the info. Sad to hear it is not officially supported but thanks for the workaround. I’ll try this out later today. But I was now looking on gitlab and apparently on KiCad 9 the workaround by editing the text file isn’t really working anymore either:
“Not visible” doesn’t mean “doesn’t work”. So you just have to test to see if invisibility makes your workflow impossible or too difficult. The only things which really must work is the gerber export.
This caused my heart to skip a beat as I’ve made use of inner layers netties (in a hacked/kludgy way) on a few KiCad design now. I just loaded one into 9.0.3 and my inter layer netties show up fine in the layout editor. One of them on layer 3 is highlighted below in the attached image.
What was ‘invisible’ was post the hand-hack, nothing would show in the footprint editor, not the PCB editor and it was this way prior to V9 too.
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Others have answered how to shift a net-tie to an inner layer. Just be aware that this “star ground” concept is very flawed. When you have two of these ICs, are you connecting the two grounds in two places? I prefer a really good ground plane in most of my designs
I wouldn’t underestimate the use of net-ties. From what I can see from DaveL post, it’s an unconventional design. If he uses it, it must be for a reason that we may not know (and he may not want to share), but there must be a reason for it.
A ti ADC that I’m designing with just at the minute says to connect the Digital GND and Analogue GND using a star connection . . . if I did it it would be for the reason that the manufacturer of the ADC told me that I should . . . not sure if that is the best advice or not, so I would have a reason also but not sure if it would be a good reason or a poor one.
I disagree, it’s not the star ground concept that is flawed. I’m very aware this is a controversial subject and generally a solid plane with smart component placement is the way to go. However there are applications which can profit greatly or are even in need of split ground planes, some of them need the tie on an inner layer. (For example in my case when designing a battery management solution with an integrated high current charging IC which also has a sensitive coulomb counter on the same IC)
Also I don’t consider it a solution to hack text files with no guarantee I will be able to properly work with my project files in the future. Because “pads are not allowed on inner layer and therefore not guaranteed to work” was the answer on gitlab.
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Easy: If you don’t follow the manufacturer’s advices and at the end the design doesn’t work as expected, then that would be a good reason.
Just modifying the footprint as explained before is enough. There is no need to tweak the PCB file. You will simply have a specific internal layer net-tie footprint that you can name as you wish and use in different projects.
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True yeah thats a lot less bad than I thought so. I guess I’ll have to live with this workaround. Does everything else work as expected on the inner layers, like copper pours and DRC?
I’m not sure about DRC. Time ago in v7 there was a net-tie DRC issue that it should be fixed in v8 and v9.
For 99% of things like SMPS and most anything ‘digital’, I agree that one is usually best served by having a GND plane that has as low as possible loop areas and R/L parasitics. This usually means as solid and uniform as possible.
However, for very low level, low frequency, sensitive analog signals, over some distance, there’s exceptions. The snippet I showed is from a design that has (96) large area PhotoDiodes feeding (96) TransImpeadanceAmplifiers followed by (96) LowPassFilters. The signals from these can be small (mVs) and need to include zero. (bipolar PSs.) The impedance of the low noise precision TIAs is very high and the signals are very low so I also use guard trace moats sans solder mask as pAs of leakage current can matter at a JFET TIA front end. The frequency of interest for these signals is DC to 10kHz with a steep LPF at ~12kHz.
All the above circuity is on a separate PCBA sandwitched to another PCBA that has the snippet that I showed. The signals named LPO… is the output of the LP filter and the TIA… goes back to the TIA ref. These signals are routed like diff pairs for minimum loop area and maximum CMR. (If I could get the PDs and TIAs on the same PCBA and very close to the associated PGAs, maybe a different story, but with a densely packed array of large area TH PDs, coupled with product packaging that called for Z axis PCBA stacks, there wouldn’t be a single common ground ‘plane’ anyway)
The component shown in the snippet is an 8CH ProgramableGainAmplifier and I have (12) of them to get the (96) channels. This PGA is also mostly a low frequency, small signal bipolar powered analog device, it just has a SPI buss for the programable gain aspect.
Anywho, I think this is OT from the OPs question. It seems to me the OP asked how to get KiCad to do things that most other tools do, not to get a lecture about how very flawed his concept is.
If things like innerlayer netties or star connections comes from ‘very flawed concepts’ why does most other tools support them? Why is it on KiCads roadmap to improve them? Why do mfgs provided parts with separate dedicated pins specifically to afford such connection schemes and with app notes including them? Rhetorical.
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I don’t recall any issues with Cu pours, but I do recall having to dismiss a whole lot of DRC complaints with them. I haven’t done any new designs using innerlayer netties using V9 yet, so I don’t know it that’s been improved from the V7/ early V8 era or not.
FWIW, I have no problem acknowledging a DRC bitch and then simply ignore it after. As said earlier in this thread, it’s the gerbers that matter, and they are fine with hand hacked layer defines.
Net-tie function can be tricky to get right with DRC - I use them for 4 wire current sensing. KiCad 8 and 8 do seem to be much more consistent as some bugs to do with thermal spokes and zone fills are now fixed.
I do use star ground concept in switch mode dc-dc converters, but you do have to be careful to route all related tracks through a single path close to this star point, to avoid radiating loops.
A 4-wire Kelvin connection is a great example. I tried to not describe my snippet example as a ‘star ground’ but rather a ‘star connection’. It’s not so much a ‘ground’ connection as it is a voltage reference connection, that happens to be at zero volts DC. Just like the sense wires in a Kelvin connection carry negligible currents and are sensitive to tiny voltages, if you keep them length matched and closely coupled (like a diff pair or twisted pair), then they’ll reject common mode noise and influence.
Now imagine you have say (96) sense line pairs you want to have Kelvin connections to a remote downstream device or DUT on a dense double loaded 8-layer PCB. It would be real nice to have those sense lines and make those (192) Kelvin connections on the inner layers, In fact it could be argued that those Kelvin connected twisted pair sense lines carrying tiny currents could be best served on the inner layers and that’s the best place for them.
I can understand the OPs concern that some potential change in Kicad’s future will render the present hack/kludge for inner-later ‘footprints’ unworkable, but I think it’s much more likely that future Kicad will give such inner-layer ‘footprints’ more proper care and capability.
I have posted a couple of my own internal-layer net ties here. I think the post is the 23rd (next to last) post on the discussion thread:
Yes these were text edit hacks.
As a power supply specialist, I think of the most common application of a net tie as connecting a feedback sense net to an output net. The sense net track can be very narrow if desired (I prefer not to make tracks too narrow if space is available) but you would typically want the power output to be much wider.due to carrying your output current.
I have also used net ties to interconnect quiet ground and power ground for an ADP1621 boost controller IC. I would agree that partitioning these grounds is not always necessary, but it does seem to be the more recommended approach.