How do I make Net Ties or Pads on inner Layers?

[DaveL]

https://gitlab.com/kicad/code/kicad/-/work_items/19127

I’ve never had a git account, but I just created one to upvote this per the suggestion. Kinda surprised it only has 19 up-votes, but I don’t know what’s considered a threshold or how upvotes are weighted. I’ll have my wife and dog create a git account too.

[davidsrsb]

This request for internal pads is a subset of a long standing request for complex stackups eg to simplify flexi-rigids

[Naib]

@DaveL

I’ve never had a git account, but I just created one to upvote this per the suggestion. Kinda surprised it only has 19 up-votes, but I don’t know what’s considered a threshold or how upvotes are weighted. I’ll have my wife and dog create a git account too.

Welcome to the world of software forges
That is one particular issue and there are at least 4 more; here is one Net ties, star routing and decoupling capacitors as first-level tool (lp:#1571930) (#2018) · Issue · kicad/code/kicad

The discussions associated with making net-ties 1st class citizens (to improve their usage, to make them more flexible) is a protracted discussion because it relies on other capabilities to be implemented
Net tie on internal layer - Layout - KiCad.info Forums. I am one of many that would <3 a more robust/flexible solution but it takes time, the complex pad stackup is a step in the right direction

[novaktamas]

Some more arguments for redesigning net-ties.

• Regardless of star-point connection, readability requires net-ties: bigger MCUs can have 20 different VDD pins…although they all are connected to +3V3, still better to read VDDD, VDDA, VDDIO, etc. instead of +3V3
• If net-tie is used at a multi-layer PCB, several footprints must be created for each internal layer, as manually edited footprints cann’t be moved to another layer with just Edit the footprint.
• If there is a footprint on an internal layer, you can use Flip side, but it mirrors the layer (eg, in an 8-layer design, the footprint will be flipped from layer 2 to layer 7. And -as there are visibility issues- you could search for the vanished net-tie footprint after a Flip command.
• If a net-tie connects two copper zones, the shape will be strange because the zone of one net will avoid the pad of the other net.
• If you want to avoid proximity warning/weird shapes of the two connecting zones or wires, you may create a large net-tie…but at dense layouts, you need as-small-as-possible net-ties, which will drop a lot of DRC errors.

I don’t know anything about the internal structures holding footprint and net data, but I think of two enhancements:

• Each net may have a list of “aliases”. Placing a track, filling zones, and DRC would take into account this list: connecting to another net, which is listed as an alias, is allowed. Aliases might be given by placing two or more net labels on a wire. In this manner, there wouldn’t be such a thing as “net-tie”.

• SMD footprint may have a “special” attribute which allows the footprint to be placed on any -even internal- layer. This would allow net-tie footprints on internal layers and buried components as well.