I second that. And the fact it works in every editor (schematic, layout, footprint, symbol) with just one rightclick away makes so simple and versatile.
I just had ChatGPT create some examples, to show how powerfull Find Similar Objects (FSO) is. This list is virtually endless and no complex search operators are needed (just set wat you want or not want):
Schematic (SCH) — smart recipes
Normalize power pin visibility
Goal: Hide VCC/GND pins on logic ICs.
FSO: Object Kind = Pin, Electrical Type = Power, Component = Same Library Ref.
Action: Inspector → Visible = False.
Standardize parameter casing
Goal: Force Manufacturer and MPN parameters to uppercase.
FSO: Components with Parameter “Manufacturer” Any (exists).
Action: Inspector → Manufacturer = =Upper(Manufacturer) (Inspector supports simple functions).
Lock critical net labels
Goal: Prevent accidental drags on high-risk nets.
FSO: Net Labels with Net = VCORE or BOOT*.
Action: Locked = True.
Bulk swap room membership
Goal: Move selected sheet’s components into a named Room.
FSO: Components, Source Document = ThisSheet.
Action: Room = MyRoom_Analog.
Unify designator placement rules
Goal: Keep designators outside sheet symbols.
FSO: Designator strings inside Sheet Symbols (Location Within Object = Sheet Symbol).
Action: Move by ΔX/ΔY or Justification to chosen corner.
PCB — precision control
Retarget only “non-rule” track widths
Goal: Bring odd widths back to rule.
FSO: Tracks where Width ≠ Rule (Set Width = Different).
Action: Inspector → Width = From Rules.
Lift micro-vias out of paste-mask pads
Goal: Un-tent vias only when they sit inside SMD pads on Top.
FSO: Vias; Layer Pair = Top-Mid, In Component Pad = True, On Top Layer = True.
Action: Tenting (Top) = False.
Normalize diff-pair members
Goal: Set width/clearance for both members without disturbing others.
FSO: Tracks, Net Class = (your diff pair class).
Action: Width = 0.1 mm, Clearance = 0.1 mm, then Length Tuning = Reset.
Bump only stubs on a given net
Goal: Find & delete stubs on a high-speed net (cleanup).
FSO: Tracks, Net = PCIE_TX*, Connection Kind = Stub.
Action: Delete or Slide.
Re-priority overlapping polygons
Goal: Set GND pour to higher priority than AGND only in a region.
FSO: Polygons in Area (use selection area) with Net = GND or AGND.
Action: Priority = GND:10, AGND:5, Pour = Repour.
Tighten keepout for courtyard breaches
Goal: Expand component keepouts only for tall parts.
FSO: Components, Height > 8 mm.
Action: Generate/Resize Component Keepout (Inspector) or add Room and apply clearance rules.
Uniform pad fillet tweak (wavesolder)
Goal: Only THT pads on Bottom to have larger solder mask expansion.
FSO: Pads, Hole Type = Plated, Layer = Bottom Side, Pad Type = Thru-hole.
Action: Solder Mask Expansion = 0.08 mm (Manual).
3D body housekeeping
Goal: Hide 3D Bodies on assembly layers for a quick 2D assembly export.
FSO: 3D Bodies, Layer = Mechanical 1/13 (your ASM layer).
Action: Visible = False.
DRC exception containment
Goal: Mark only intentional neck-downs as “Waived”.
FSO: Tracks, Net = VBUS, Min Width Violating = True, Within Room = “USB_PWR”.
Action: DRC = Create Waiver (context) with note.
Flip-side text unification
Goal: Force all Bottom Overlay designators to mirrored + 1.2 mm.
FSO: Strings, Layer = Bottom Overlay, IsDesignator = True.
Action: Mirrored = True, Height = 1.2 mm.
Via stitching, but only inside copper islands
Goal: Stitch GND islands beneath RF can.
FSO: Regions/Polygons, In Component = RF_Shield, Net = GND.
Action: Add Stitching Vias (Inspector) → pitch and grid as required.
Variants / BOM / assembly
Variant: set Fitted by class
Goal: Unfit all components in class DEBUG_ONLY for Release variant.
FSO: Components, Component Class = DEBUG_ONLY.
Action: Fitted = False (in Variant Manager through Inspector).
Normalize supplier links
Goal: Clear obsolete “Supplier 2” only where stocked “Supplier 1” exists.
FSO: Components with Parameter “Supplier 1” Any & “Supplier 2” Any.
Action: Supplier 2 = (blank).
Assembly side sanity
Goal: Ensure LEDs on front only.
FSO: Components, Comment contains “LED”, Layer = Bottom.
Action: Flip (or relocate) or Mark Variant Unfitted.
xSignals / timing
Retarget one interface timing quickly
Goal: Re-apply length target to all xSignals in DDR3_DQS0 room.
FSO: xSignals, In Room = DDR3_DQS0.
Action: Matched Length Target = 40.0 mm, Tolerance = ±0.5 mm.
Fix serpentine amplitude only on over-tuned lines
Goal: Reduce meanders that exceed amplitude.
FSO: Length-Tuning Objects, Amplitude > 0.8 mm.
Action: Amplitude = 0.6 mm, Gap = 0.2 mm.
Mechanical / documentation
Regenerate paste-mask for fine-pitch only
Goal: Halve paste for <0.4 mm pitch parts.
FSO: Components, Pitch < 0.4 mm.
Action: Paste Mask Expansion = Rule/Custom, Paste Cutout = 50%.
Tight assembly drawing
Goal: Show only RefDes + Outline on ASM layer.
FSO: Component Outlines on Mechanical 13 + Designator strings.
Action: Visible = True; hide everything else on that layer via FSO.
Power moves (FSO + Inspector tricks)
Scope by “Same”, then push to Query
In FSO, tune fields (e.g., Net Class = Same, Layer = Same), click Create Expression → save in PCB Filter for one-click reuse later.
Delta-move precisely
After FSO selection, in Inspector use ΔX/ΔY to nudge a whole class (e.g., shift all bottom-side designators by +0.2 mm Y).
Conditional numeric edits
Inspector supports From Rules and numeric =Max/Min() style helpers; e.g., set Width to =Max(Width, 0.15mm) across selection.
