I’ve drawn the left channel of my driver schematic and I’ve placed the components so far.
What I’d LIKE to do is copy the left channel schematic and make the right channel and then MIRROR the PCB layout of left for the right channel.
Is it possible to do that in KiCad?
PCB layout halfway completed for reference:
Exact mirror images are simply not possible when you use any footprint that is not symmetrical in it’s function. This excludes nearly all footprints with more then two connections.
But you can come pretty close in a few simple steps:
After these 4 simple steps, the copper is correct, but all footprints are still on the wrong side of the PCB, and they are also copies that have no connection to the schematic, and you’ll have to fix that too. You will also have to reroute some of the tracks, for example to get your 2N2222 back on the front of the PCB.
Also, make sure you make a backup before you do this. This will allow you to easily revert if you make some silly mistake during this process.
Here is how I copy + paste entire sections.
Temporarily setting the measurement to a high level (2.5400mm = 0.1in)
with snap to grid on ensures accurate placement.
Obviously, I’m only wanting to mirror the positions of components, but I wondered if there was a way to maintain the connection with the schematic as follows:
Duplicate the left channel schematic, verify common B+ and ground busses. Then transfer to the PCB the updated right channel. Finally, have a way to make the right channel layout symmetrical with the left, other than a time consuming part by part placement that might not be accurate.
I’ll save my work and try your 4 step method and see how that works out.
Well, that gave the symmetry, but doesn’t take into account the orientation of parts and connections. Maybe there’s no alternative but to hand place all the parts and try to mirror the layout by hand, but I’d thought I’d ask just in case I missed a nifty feature somewhere in KiCad.
After the “4 step process”, you have copies from the left channel, and (I assume) also “real parts” for the right channel. It’s not so difficult to delete the copies, then grab the new parts for the right channel by a pad, and snap them to the existing track ends. It’s also easier if everything is on a relatively coarse grid.
KiCad has a very nice feature in which you can use hierarchical sheets to add more instances of a section of your project. You can also use Schematic Editor / Tools / Annotate Schematic with the Numbering: / First free after sheet number X 100. If you use this method, then the RefDes of the left & right channels has a fixed offset, and this allows you to:
You did not do step 4). The swapping of the copper layers.
I don’t understand:
First, if you do the layer swapping of the copper, then you have a visual match in track colors, this makes it less confusing to look at the PCB.
The layout IS mirrored, it’s only not so obvious because you have not swapped the layers between top/bottom.
A quick way to get all the footprints for the right channel to the front is:
But do note that you are still doing this on the copies, and these are not connected to the schematic. Fixing this is a separate step I already explained.
Maybe because I got confused and did step 4 twice, once for the blue to red layer and once again for the red to blue?
At any rate, I’ve ended up spending several hours just manually placing parts, but the routing is completely different from the left half, even though I painstakingly mirrored everything…
I’ve got nets that refuse to let me connect them, too:
This is what the board currently looks like. Almost there, except for several unconnected nets:
Did you notice that the “swap layers” lists both copper layers?
Huge waste of time, you can work hard, or you can work smart. If you just had a look at the results of the “swap layers” or spend some more time experimenting and learning how it works, you would have learned to use KiCad more effectively.
To me it also feels I’m wasting my time here. I hope you’re happy with your result, but I’m not putting more time in it.
Yes, I noticed that menu and that’s why I swapped layers twice- once for each side.
If you think helping others is a waste of time, why are you here?
I spend probably between 20 and 30 minutes on this thread for a task that I would have done in 5 to 10 minutes (inclusive fixing the symbol to footprint associations). And your response is that you spend hours, and did something else in the end, and that is quite discouraging. So yes, I am here to help, but I’ve also learned I can’t help everyone.
Would it be possible for you to post/upload your schematic?
Some additional considerations.
IF you are planning to use the ECC83 (aka 12AX7A)
with high voltage B+ 300V and standard 6.3V Filament Voltage
pins (4+5),9 your copper traces will need to be
of sufficient width:
Recommended minimum 0.032in, 0.8mm for input signal pins 2,7
and cathode pins 3,8
0.05in, 1.2mm for Plate B+ Voltage pins 1,6
0.1in, 2.5mm for Filament Voltage/Amperage pins (4+5),9
It appears you utilized auto-route to begin with,
based upon the ‘cosmetic symmetry’ pcb component layout.
Near proximity of Filament, Cathode, Grid, Plate traces
will cause extreme low signal/noise ratio.
HERE IS AN EXAMPLE OF MY SIMILAR TUBE/VALVE PREAMP PROJECT
WITH ALL BOTTOM COPPER TRACKS LAYOUT
PCB TOP
PCB BOTTOM
Layouts with footprints > 2 pads will hardly ever be symmetrical. Choosing the refdes can simplify the placement task. For example use 1nn for left channel and 2nn for right channel. Together with a grid it makes it obvious where the other channel’s footprints have to go. The asymmetrical footprints for tubes and transistors can be dealt with separately.
I’m not sure what good would uploading my proprietary design here would accomplish.
I originally set the design rule for a 1.0mm trace and found that auto route would get stuck. A handful of traces done and endless loop of iterations after that. I had to go with .75mm to get it to even route the PCB. I’ll specify 2 oz copper at manufacture time to help. The traces that need to be large are the filament lines, as they carry 600mA in this configuration.
Spacing away from filament lines is a concern. Most of the lines cross at 90° angles, so crosstalk would be minimal. I plan to take a closer look at the PCB traces to see if any sensitive lines are too close to something that could cause positive feedback or noise.
I’m doing various iterations of the circuit to see what works best. I may try to increase specific traces widths and then re fill the groundplane. Sometimes I get a violation when increasing the width of a trace, so it’s a case by case basis.
While I appreciate your efforts, you must understand that I am testing different methods. This is all new technology to me, as I come from a point to point wired world and in many ways, I’m still stuck in the 1950s in that regard.
While you have more experience with KiCad and have formed a lot of neural connections on what features are available and how to use them, that is largely in the realm of the ‘to be discovered’ realm for me at day four of using the software.
The PCB is a mess in that there’s several traces with “no net” on them. The larger issue is that the importation of LTspice circuit wasn’t a perfect, no further work needed, situation. I’ve to figure out the footprints and nets and try to clean up the mess of errors that DRC spits out.
I may make another copy of the project and try your method again and see if I can figure out where it went astray.
What I did was make a copy of schematic and rename designations with a -B so I could have the same numbering, ie. R1 and R1-B. That helped with quickly IDing the components and placing in a mirror image fashion to the left channel.
I’m not sure, but using suffixes like B might confuse KiCad into thinking they are units of a symbol and trigger spurious ERC messages. The 1nn and 2nn scheme can be easily done by using hierarchical sheets.
Strange that you encounter track width issues. As far as I can see there is plenty of room.
The clearances on your B+ lines look a little tight, as do the widths of your heater lines.
You can modify the widths of single tracks; they don’t all need to be the same. You can also assign netclasses to your B+ nets and give them a larger clearance than the rest of the board.
