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[BUG] Font thickness varies on the PDF/SVG output
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1
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530
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May 27, 2023
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Overlapping copper pours no longer connect
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28
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1698
|
May 27, 2023
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Showing OP voltage and current data in EESchema V7.99 nightly builds-How?
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18
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2754
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February 26, 2023
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[solved] Problem with a 3d model not showing up
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5
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1487
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May 27, 2023
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Lines on margin layer cut copper pours
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14
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1605
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May 27, 2023
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Get Pin name with python script
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5
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741
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May 27, 2023
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How to route track on USB C Receptacle B Row?
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5
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1881
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May 27, 2023
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How to renew fp-lib-table and sym-lib-table?
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2
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1433
|
February 26, 2023
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Error: Board has malformed outline (not a closed shape)
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12
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4122
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May 27, 2023
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Symbol Fields Table in Hierarchical Schematics ... can't limit scope to current sheet
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20
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2163
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May 24, 2023
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Open hardware CM4 module
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10
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3731
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May 26, 2023
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Ubuntu 7.0 testing builds
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1
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994
|
February 23, 2024
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FOSDEM 2023 talks
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17
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1770
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May 3, 2023
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Schematic Editor: Table Insert Tool to Arrange Data
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4
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1591
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May 26, 2023
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How does the Kicad 7 cable size calculator work?
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11
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1178
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May 26, 2023
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Anybody looked at or used Flux.ai?
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13
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16931
|
May 25, 2023
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How do you lock PCB holes
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17
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1565
|
May 25, 2023
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Copper pour misses a "stripe" when corner smoothing active
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2
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431
|
May 25, 2023
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Simulation Attribute Visibility in V7
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1
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520
|
February 24, 2023
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Cursor behavior
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4
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562
|
May 25, 2023
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Probing Currents in V7
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1
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605
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February 24, 2023
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KiCad 7 3D models of a KICad 6 imported file
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11
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2935
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May 25, 2023
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Reopen: .kicad_sch and .kicad_pcb files now default to no group or world read on Linux
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2
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753
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February 24, 2023
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Filter synthesis and network analysis
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7
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1286
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May 25, 2023
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[Python Bindings] Problems accessing built-in colors (KiCad 7)
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23
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1303
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May 25, 2023
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Improve title of Python bindings pages; low-hanging fruit!
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1
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666
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March 26, 2023
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6.0.x → 6.99 pcbnew python bindings changes
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1
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2091
|
March 30, 2023
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How do I get component values on the manufactured PCB?
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18
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10324
|
February 24, 2023
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V7.0 Overflowing Opening PCB
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8
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1523
|
May 25, 2023
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Add pins to schematic only (virtual pins)
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3
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1054
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May 24, 2023
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