Just upgraded from KiCad 5. Previously, overlapping copper pours on different nets would raise a DRC error but would still connect to each other.
Now, the zone fill building tool forces them to be separated.
How do I turn off this “feature”?
I suspect this falls into the bucket “Why are two nets treated like two nets and not one net, like I want.”
Either name the two nets the same, or use a Net Tie.
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Yes, the fill is the net tie. “Net tie” footprints are poorly conceived and result in noisy circuits.
Much better to draw exactly what net tie I need, and easily shift its shape as the layout is tweaked through the design process.
KiCad 5 allows this. 7, apparently, does not, and this is a problem.
I’m not sure what you mean by:
KiCad’s net ties are just a few simple generic examples. Net ties tend to be very project specific, and it has always been intended to make your own to your own specifications.
In KiCad V5, graphical items on a copper layer were not recognized by DRC at all, and this is a very bad thing, and later KiCad versions improved on this. At the moment you have to include the “net tie” keywords (without quotes) in the description of a a footprint:
(I don’t know which of the two is mandatory). This is a hack to emulate the older net tie behaviour and suppress DRC violations for net ties.
A real solution is in the working, there are several open issues related to net ties on gitlab.
To add on, I will note that this behaviour is directly in contradiction to the KiCad 7.0 documentation:
which reads (in highlighted, bold font, in a special red box, with a warning sign):
Zones with the same priority level will never keep clearance from each other, even if they are assigned to different nets! The design rule checker will report these short-circuits, but they will not be prevented by the zone filler.
with further clarification in a nearby paragraph, describing exactly the behaviour I want:
Two zones on the same layer with the same priority level will overlap (short-circuit) with each other.
I cannot reproduce this documented behaviour.
That was very weird behavior, and I don’t know if it ever worked properly. I guess nobody updated the documentation afterward.
One option for you is to not use net ties at all, and just use multiple overlapping zones (or a single more complex one) all connected to the same net.
Another option is to use a Rule Area and then use it to narrow a zone. The Keep out copper fill is disabled by default, so make sure to set that checkbox.
In a more general sense, I wonder what your PCB looks like. Separating different GND planes is mostly a very stubborn and not very useful, or even bad practice.
Ground in PCB Layout - Separate or Not Separate? (with Rick Hartley)
Ground in PCB Layout - Separate or Not Separate? (with Rick Hartley) - YouTube
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That was very weird behavior, and I don’t know if it ever worked properly.
It worked fine in KiCad 5. Pours would render properly and DRC would flag it as an error.
Separating different GND planes is mostly a very stubborn and not very useful, or even bad practice.
Yes, exactly.
But having separate labels for different parts of your ground plane is very useful.
The board manufactures the same either way, but having a clear marker that “this decoupling capacitor belongs with the analog stuff” is very helpful for layout. Otherwise, you just end up trying to properly locate fifty identical 100n capacitors that all connect to 3V3 and GND.
Also, there’s at least one reason for a ground plane trench: running your digital power through a common-mode choke to pass EMC testing. Kind of defeats the purpose of the “common mode” if the current return path is just anywhere.
I can confirm that the behavior you expect happens in 6 but not in 7.
It seems like zones in 7 might be following the DRC rules (which is new.) If I set the net class to a clearance of 0, then two zones with the same priority will overlap.
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@baldengineer I can get an “almost-overlap” by setting clearance override to zero or netclass clearance to zero, but it’ll still fillet on the corners and force a five micron gap:
In KiCad V7 the simplest way to go is probably still to use a net tie.
Here I placed a simple (default) net tie between two planes (thermal reliefs can be disabled easily, but I left them to show the net tie shape).
Then hover over the net tie and press [Ctrl + e] to load it in the footprint editor:
Then select the rectangle between the pad, and drag the handles a bit around:
Then just close the footprint editor. It asks you whether to discard or save your changes, make sure to save them back to the PCB:
Result:
Well, that’s inconvenient. Trial and error until you get the exact shape you need, I guess…
The board I upconverted to 7.0 has quite a few overlapping planes on quite a few layers that will all now need to be fixed. TVS diodes pointing at ‘power ground’ in the analog input region now need to change on the schematic to match whatever part of the ground plane they actually end up on. (And change again if they have to move.)
When before I could just draw a zone and be done with it.
I’ve raised an issue here: Overlapping same-priority zones no longer short-circuit as described in the manual (#14069) · Issues · KiCad / KiCad Source Code / kicad · GitLab
I’m not sure but my first guess would be that the documentation will be updated without a code change.
Not necessarily.
In the example below, I did:
- Draw a kite with: PCB Editor / Place / Draw graphical Polygon.
- Copy the kite to the clipboard.
- Hover over the net tie and press [Ctrl + e].
- In the footprint editor, delete the rectangle in the net tie.
- Press [Ctrl + V] to paste the graphical polygon.
- Close the footprint editor and [Save] changes back to the PCB.
Apart from that, instead of “guessing” you can also use the measurement tools and make some notes on how big you want things, or have the PCB and Footprint editors open at the same time. (Multi monitor works great for this).
Paul, thanks for the suggestion. I got to the point of drawing the net tie and discovered I can’t put footprints on interior layers. How can I get around this to tie an interior ground plane?
Actually KiCad supports SMD pads on inner layers, but not in the level of UI when footprints are created. You can manually edit the footprint file or the board file and just change the layer of the pad and the non-pad copper shape. (Remember to remove the mask and paste layers from the pads.)
(fp_rect (start -1 -5.75) (end 1 7.75)
(stroke (width 0.2) (type solid)) (fill solid) (layer "In1.Cu") (tstamp 2b0cf023-cd8f-4153-a15b-d75eaa108009))
(pad "4" smd roundrect (at -0.18 7.58) (size 2.286 1.524) (layers "In1.Cu") (roundrect_rratio 0.25)
(thermal_bridge_angle 45) (tstamp a4d99cc6-ee1e-4cf3-944e-6062ff8be303))
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Via?
How would you like to place footprints on the inner layers? And how would it be manufactured?
I just told.
SMD footprint pads are just copper. I think board manufacturers can put copper on inner layers. 
It would be more difficult to assemble components there…
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It’s a net tie. It’s just copper. But KiCad 7 is making this process inordinately hard as compared to KiCad 5 in which you could just overlap two zones.
I think that net-tie could be special filled area with check-boxes for each of layers you have.
I don’t know if filled polygon (with no net attached) placed at copper layer will overlap with zones or not.
I don’t know if filled polygon (with no net attached) placed at copper layer will overlap with zones or not.
The zone pour will also maintain clearance with a copper polygon.
So the only solution is to do it as a last design step (after DRC) and avoid zone pour afer it