I have previously used the Margin layer to indicate the required setback from the board edge for component placement. Importing a KiCad 5 project into KiCad 7 and now copper fills are bisected by the margin layer.
The error is propagating all the way into GERBERs.
Is there any way to turn this off? Margin layer is not and has never been intended to be used in manufacturing.
I can’t speak for v5, but for v6+v7 the margin-layer behaves the same. It’s described as “edge.cuts setback” and therefore all layers respect the edge.cuts <-> copper clearance. So it’s correct that the zone-fills don’t overflow the margin-line.
As a note (difference between edge.cuts / margin):
for lines on the real edge.cuts layer the clearance is meant from copper to edge.cuts-center line
for lines on the margin layer the clearance is calculated from copper to outline of margin-line
When I started to read about KiCad (4.0.6 times) the documentation was practically from V3 yet. I have read there that Margin layer has some special meaning that I didn’t fully understood so for safety I have never used it.
Me too.
I don’t understand setback in PCB case. I can suppose something but I’m not sure.
Is it something that can be done with Rule area?
If yes - the idea of back compatibility is great, but who knows, may be sometimes it is good to delete old concept tools (replaced by more powerful) just to simplify things.
just for information two example cases where I use the margin layer:
drawing a bigger circle around a hole to get more isolation
drawing a simple line/rectangle to remove copper (and fills) from a particular board area
drawing margin lines in the middle of the board to bisect GND-fills (power-part, digital controller part) and limit connection between both parts to only a small board-area
I see the margin layer as edge.cuts without a real cut. It’s faster to draw and later faster to modify than the other more complicated (but also more powerful) tools.
I agree that all these cases can also be solved with other tools, but the margin-layer is simple and fast usable. The other tools required would be draw a rule area (complicated for arcs/circles, especially complicated to modify later), to use custom rules, to use complicated zone-outlines or multiple zones.
“Board edge setback outline” indeed. My assembly house has different setback requirements for SMD positioning, traces, or copper pours. Furthermore, the SMD positioning is dependent specifically on the location of the package and leads, which is not the same as the courtyard…
Ideally, margin would work with DRC to determine if any of those constraints are broken, but I suppose that’s a feature request and not a bug.
I would be surprised if a 0.05mm (or whatever line thickness) trench under a margin line is “intended behaviour”… it’s a margin, one side is in and one side is out. As written, the phrasing “board edge setback outline” certainly does not imply it should be a polygon.
@mdsaund : the copper (zone fills as well as tracks) takes the “copper to edge” clearance (from board-setup->design rules->constraints) as distance between copper and all elements on the margin layer.
I had keep-out layer in Protel. When reading KiCad documentation (it was mainly about V3) I didn’t understood that Margin layer is Protels keep-out layer even I was searching for keep-out. As I remember I even asked at forum but was directed to use Rule Area.
But as I read this thread it looks that margin layer started to work with V7.
This is exactly the intended use of the margin layer. It goes way back in Kicad history, before we had a lot of the more sophisticated features the current Kicad has.
You can now use Custom DRC Rules to handle as many different types of setbacks as you want. And there are now lots of user layers that you can use to mean whatever you want them to.
Intended to be used with polygons as a copper keepout? The “outline” wording should definitely change then – “outline” refers to a line, not an area.
