How to get "sticky" tracks when doing component placement?
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5
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604
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April 29, 2024
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All polarized capacitors from the footprint library have two centers?!
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9
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2070
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April 29, 2024
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Via rules - how to
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16
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1362
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April 29, 2024
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What setting causes this weird Track Posture issue?
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9
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963
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April 29, 2024
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Re-generating the same pcb stage from a copy of schematic stage
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3
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596
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April 29, 2024
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"Update PCB from Schematic" greyed out after crash
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3
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1193
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April 29, 2024
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KiCad Traces to Schematic Not correct
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13
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633
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April 28, 2024
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Cannot parallel up power chips. Generates Errors
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9
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788
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April 28, 2024
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Gerber Not Generating Proper Output Files
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7
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1042
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April 28, 2024
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SODIMM-200 Layout
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4
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1321
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April 27, 2024
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Productivity suggestions for locked objects
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6
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628
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April 27, 2024
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Renumbering footprint?
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5
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883
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April 27, 2024
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Origins and Relationship To Array/Other
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1
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450
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April 27, 2024
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Ground and Power Busses share net names
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5
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924
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April 27, 2024
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Features - good idea, but bad execution
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12
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965
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April 27, 2024
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Custom DRC distance rule with exception
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16
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1099
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April 27, 2024
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PCB Editor: Displayed KiCad version length is too long and overruns into date field
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2
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615
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January 28, 2024
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How to select vias along a net track route?
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7
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783
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April 27, 2024
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Crash on M1 MacBook Pro w/ Sonoma
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22
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2226
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April 27, 2024
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Renaming "Create Footprint Wizard" Footprints _before_ exporting into a library
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19
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1088
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April 26, 2024
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[Solved] Pad and Copper Fill Not Connected
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32
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3172
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January 27, 2024
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Througholes not opening up on Gerbers
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23
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1359
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April 26, 2024
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How to move values?
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27
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1240
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April 26, 2024
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Newbie and jumpers
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18
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3389
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April 26, 2024
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Circular traces?
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21
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3552
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April 26, 2024
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Can I get copper on just one side of a pad?
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20
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2293
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April 26, 2024
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NC pins making a net
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9
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853
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April 26, 2024
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PCB Antenna Footprint Design and DRC
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5
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2049
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April 26, 2024
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PCB Design
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5
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897
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January 26, 2024
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Connect Track To Nearby Pad/Via
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2
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756
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April 25, 2024
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