Via rules - how to

[glenenglish]

I’m trying to add a via rule to custom rules. (I have the gui set rules to 0 but custom rules always override others so that’s fine)
Now, here is the problem :

(rule "override rule vias"
(condition "A.Type =='via'")
(constraint via_diameter (min 0.7mm)  (max 2.0mm))
(constraint hole_size(min 0.3mm)  (max 1.6mm)))

In BoardSetup-DesignRules-Predefined-sizes
If I set a via size that is 0.5mm dia / 0.2mm hole,
then if I setelect this via in the tool bar , and then place a via , it permits this.
The rule should prevent me from placing it.
–If it only picks it up at forced DRC time, then I will have a mess to clear up later (productivity issue) .
-g

[baldengineer]

It’s the same behavior as when you set up the constraints in the constraint dialog. Why would a custom rule be different?

[glenenglish]

Well, the custom rules override the dialogs.
I might have 10 rules about different vias for different netclasses
If I select a via in the via drop-down from choices, then,
if I attempt to place a via and make it part of a net that has a rule that excludes it , then the tool ideally should not place, throw an error or something. It needs to stop me choosing a via that violates the rules.
A manual DRC does flag the violation, so the rules do work. But it results in cleanup work.
Just like when the tool in the yellow bar at the top informs you it could not place a via due to a location violation .

[baldengineer]

Yes, they override the dialogs… when the DRC checker runs.

Does use netlcass sizes not work in this case?

[glenenglish]

I could use netclass size, but netclass size only permits one size of via, (or am I misunderstanding available functionality ?) where usually you might want to have two go-to vias , one when geometry is relaxed, and another for when things get tight.
so I would use. so the netclass via dialog is not suitable for my case.
hence

(rule "rule via for netclass XYZ"
(condition "A.Type =='via' && A.Netclass == 'XYZ' " )
(constraint via_diameter (min 0.7mm) (opt= 0.8) )
(constraint hole_size(min 0.3mm) (opt=0.4) ) )

Usually I would only use Netclasses and via assignment when I have specific requirements like back drill etc. it depends how many nets and netclasses I might have.

I think the conclusion here is I would like some of the batch DRC checks to be selectable as online DRC.

[mf_ibfeew]

if I attempt to place a via and make it part of a net that has a rule that excludes it , then the tool ideally should not place, throw an error or something. It needs to stop me choosing a via that violates the rules.

The rule system is currently not 100% coupled to the router engine.
See for instance these discussions / gitlab issues:

Incomplete integration of Custom Design Rules into interactive router

I’ve setup custom design rules for a 6 layer board with controlled impedances for differential pairs (PCIe Gen 4 and DisplayPort). I had hoped this would make routing a lot more streamline, sadly, a lot of the constraint seemingly are only for DRC and are not actively enforced during interactive routing, and some are erroneous. What does work: All clearances with simple conditions are applied during routing. This is already a big upgrade for multiple layers compared to before custom rules exis…

Custom Design Rules not properly integrated with interactive router (#15449)...

[glenenglish]

Thanks for the link to the post.
Yes, Seneral and I are on the same planet it seems .
Need online DRC selectable.
You can’t put everything in the Online mode, it slows the tool down too much.
In Altium for reference, this is how it is done : Rules have a category assigned to them :
This is the Batch or Online rule assignment dialog.

etc

this is not new stuff, been there since 1991. old.
this is how rules are done, each line is drilled down into its own dialog page.

[baldengineer]

@glenenglish

Yes, Seneral and I are on the same planet it seems .

Then make sure you up-vote the associated issue on Gitlab and add any additional context to help the developers track the need.

[Seneral]

@glenenglish @baldengineer Actually, I did some major fixes for this already, but they haven’t been merged. I’ll update to the newest commit today (if I remember, else ping me later this week).
Though anecdotally I did face a crash using the new code, though I couldn’t pin it down. But the half hour or so it worked, it was a sweet relief from all the pain the routing gave me before with complex custom rules.

Addressed constraint discrepancy issue #15449 (!1687) · Merge requests · KiCad...

[glenenglish]

wonder what the crash was.

[Seneral]

Yep, have screenshots of it there during debugging, but couldn’t figure it out since there were no tools (as in, no ids or other ways to have some code identify the case and break, it’s just one call into that subtree of thousands per frame).

[glenenglish]

mmmm
I’ve read the github discussion, you’ve been in-deep.

[glenenglish]

Altium have tried to fix this very issue (pin-diff pair initial fanout) and clean it up for years and years, and it still isnt perfect. It is a tough nut to crack. I guess u see my push for the router / placement engine to have selectable things it cares about in real time.

[Seneral]

I’m not actually a electrical engineer by trade, so no, I don’t know what would improve it - all I did was fix the router to respect DRC rules. For me, that makes fanout already possible with my current build. Just updated my repo, so if you want, I invite you to build it yourself and see if it works for you:

Files · probe-sizes · Seneral / kicad · GitLab

Any further recommendations, please do tell, I’m not certain what would be needed (nor can I guarantee I’ll find time to implement it for that matter)

[Seneral]

For reference, 6 layers with tons of custom rules, fanout:

[glenenglish]

which KICad version is that ?