We are currently using KiCAD to layout an 8 layer PCB layout with a BGA footprint.
One question came up regarding the annular rings for vias in inner layers:
If we do not have a track connected to a via, the annular ring should be set to a minimum value. This would help us to reduce the internal resistance of a surrounding copper area.
Some other PCB tools offer different settings for the annular ring width used for the outer and inner layers (e.g. Inner Annular Ring and Outer Annular Ring).
We have found nothing similar in KiCAD: There is only a single setting for the annular ring width for vias, used for inner and outer layer. Do we have overlooked something? Maybe there is someone who knows another trick?
We have used the latest release 4.0.0 RC1.
There have already been a similar discussion some years ago (see https://groups.yahoo.com/neo/groups/kicad-users/conversations/messages/13007), but the tricks does not work anymore for the current release of KiCAD…
Please have a look at the green copper area VDDSOC_CAP in the picture below. The idea is to reduce the annular ring of the surrounded vias, not connected to a track.