Hi @Gerrit ,
if you want annular ring for inner layers smaller than outer layers you can trick the board adding something similar to the topic at
nicer via stitching
you make a via module as following:
Case#1
(module via_annular_th (layer F.Cu) (tedit 561EB1CE)
(fp_text reference AN_V** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(fp_text value via_annular_th (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers F&B.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.75 0.75) (drill 0.6) (layers *.Cu))
)
then you import it in module editor and add to the board assigning the net.
if you need the opposite (inner vias bigger than outer vias) you can do a similar trick, but the DRC will give violation (so you should route disabling DRC)…
(the code is for e.g. 4 layers board)
Case#2
(module via_annular_th (layer F.Cu) (tedit 561EB1CE)
(fp_text reference AN_V** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(fp_text value via_annular_th (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(pad 1 thru_hole circle (at 0 0) (size 0.75 0.75) (drill 0.6) (layers F&B.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers In1.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers In2.Cu))
)
the easiest way it would be to add vias module also in schematics, so you will get them loaded in pcb, with all net name assigned
I have exaggerated the diameters to see better the differences
Let me know if I have understood correctly the requirements…
Maurice