Setting pads of vias in inner layers

[wykys]

Hi,
I am designing a four layer board with BGA.
I need to remove unused pads from vias to have more space for routing.

I’m using the current night build.

Demonstration of interfering unused pads.

I came across an older thread since 2015.
However, I am not satisfied with the proposed solution, so I would like to ask what are the options in the current version.

Optimizing Annular Rings of Vias in Inner Layers

We are currently using KiCAD to layout an 8 layer PCB layout with a BGA footprint. One question came up regarding the annular rings for vias in inner layers: If we do not have a track connected to a via, the annular ring should be set to a minimum value. This would help us to reduce the internal resistance of a surrounding copper area. Some other PCB tools offer different settings for the annular ring width used for the outer and inner layers (e.g. Inner Annular Ring and Outer Annular Ring). …

During Googleing, I came across how easy it is to solve Altium.
https://www.altium.com/documentation/altium-designer/pcb-dlg-removeunusedpadsoptionsunused-pad-shapes-ad

[hermit]

I think what you are referring to would be considered board stack up which is not currently available. Files are text based so you could probably change things there.

[Rene_Poschl]

@hermit

I think what you are referring to would be considered board stack

Not really. It would be called pad stackup.
Board stackup handles the general composition of the board itself (how many layers, what are the exact properties of each layer especially dielectrics, how thick is every layer, …) Board stackup tools are already in KiCad nightly and will therefore be in version 6. Pad stackup might however be postponed to version 7 if i remember correctly.