Optimizing Annular Rings of Vias in Inner Layers

Layout
1

We are currently using KiCAD to layout an 8 layer PCB layout with a BGA footprint.

One question came up regarding the annular rings for vias in inner layers:
If we do not have a track connected to a via, the annular ring should be set to a minimum value. This would help us to reduce the internal resistance of a surrounding copper area.
Some other PCB tools offer different settings for the annular ring width used for the outer and inner layers (e.g. Inner Annular Ring and Outer Annular Ring).
We have found nothing similar in KiCAD: There is only a single setting for the annular ring width for vias, used for inner and outer layer. Do we have overlooked something? Maybe there is someone who knows another trick?
We have used the latest release 4.0.0 RC1.

There have already been a similar discussion some years ago (see https://groups.yahoo.com/neo/groups/kicad-users/conversations/messages/13007), but the tricks does not work anymore for the current release of KiCAD…

Please have a look at the green copper area VDDSOC_CAP in the picture below. The idea is to reduce the annular ring of the surrounded vias, not connected to a track.

649Ă—589 24.7 KB

2

Hi,
you can link an uploaded image to dropbox (or similar)

3

Hi @Gerrit ,
if you want annular ring for inner layers smaller than outer layers you can trick the board adding something similar to the topic at
nicer via stitching
you make a via module as following:
Case#1

(module via_annular_th (layer F.Cu) (tedit 561EB1CE)
  (fp_text reference AN_V** (at 0 0.5) (layer F.SilkS) hide
    (effects (font (size 0.2 0.2) (thickness 0.05)))
  )
  (fp_text value via_annular_th (at 0 -0.5) (layer F.Fab) hide
    (effects (font (size 0.2 0.2) (thickness 0.05)))
  )
  (pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers F&B.Cu))
  (pad 1 thru_hole circle (at 0 0) (size 0.75 0.75) (drill 0.6) (layers *.Cu))
)

then you import it in module editor and add to the board assigning the net.

if you need the opposite (inner vias bigger than outer vias) you can do a similar trick, but the DRC will give violation (so you should route disabling DRC)…
(the code is for e.g. 4 layers board)
Case#2

(module via_annular_th (layer F.Cu) (tedit 561EB1CE)

(fp_text reference AN_V** (at 0 0.5) (layer F.SilkS) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(fp_text value via_annular_th (at 0 -0.5) (layer F.Fab) hide
(effects (font (size 0.2 0.2) (thickness 0.05)))
)
(pad 1 thru_hole circle (at 0 0) (size 0.75 0.75) (drill 0.6) (layers F&B.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers In1.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.9 0.9) (drill 0.6) (layers In2.Cu))
)

the easiest way it would be to add vias module also in schematics, so you will get them loaded in pcb, with all net name assigned

I have exaggerated the diameters to see better the differences

1082Ă—853 96.1 KB

Let me know if I have understood correctly the requirements…
Maurice

4

And know he want’s them annular rings to re-size depending on if a track connects to it on a layer or not.
For better understanding see this drawing of mine:

800Ă—800 45.9 KB

@Gerrit
Have you tried to play around with the Design Rules Editor settings already (in pcbnew)?
I think if you would design a via with the smaller annular rings as a base to work with as a footprint and then set up a net class/track class with a different via diameter it should be possible to get the behavior you desire?

5

I played around with this a bit and used a buried via with a custom footprint via that has got small annular rings on all 8 layers. The kicad_pcb file looks like this for the important bits:

…
(module Footprints:z_via (layer F.Cu) (tedit 561F088E) (tstamp 561F1027)
(at 141.5 98.5)
(fp_text reference REF** (at 0 0.9) (layer Cmts.User) hide
(effects (font (size 0.2 0.2) (thickness 0.02)))
)
(fp_text value via (at 0 -0.9) (layer F.SilkS) hide
(effects (font (size 0.3 0.3) (thickness 0.03)))
)
*(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers F&B.Cu .Mask))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In1.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In2.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In3.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In4.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In5.Cu))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In6.Cu))
)
(segment (start 142 99.5) (end 141.5 98.5) (width 0.25) (layer In6.Cu) (net 0) (tstamp 561F1058) (status 800000))
(via blind (at 141.5 98.5) (size 1) (drill 0.4) (layers In3.Cu In6.Cu) (net 0) (status C00000))
(segment (start 141.5 98.5) (end 142.5 98) (width 0.25) (layer In3.Cu) (net 0) (tstamp 561F105B) (status 400000))
…

And in 3D it looks like this:

800Ă—476 68.7 KB

I don’t know why it makes the annular rings on the layers in-between the start and end layer for the buried via big as well, but this might be able to be solved by some programmer more easily than any other workaround?
Maybe there is some option in the code somewhere to omit extra annular rings on other layers?
It seems to be working for the layers above and below the buried via, so why shouldn’t it for the ones in between?

6

[oops] - I deleted my previous post because I can see now exactly why those inner pads are large. The blind via spans layers 3-6, so all those layers will have the annular size of the blind via.

Anyway, we’ve known for a few years now that KiCad desperately needs a padstack and editor but so far no one’s had the resources to put into it.

1 Like
7

as I posted a footprint module with different size pads is required…
(it is possible also avoiding blind vias)
I wouldn’t put *.Mask on this annular vias
and moreover you’ll get a DRC violation…
so it is a dirty trick :wink:
we will wait for a legacy padstack and editor…

8

OK, kick out the inter-layer pads and have just a simple footprint for a through hole like this:

(module z_via (layer F.Cu) (tedit 561F5CF9)
(fp_text reference V101 (at 0 0.9) (layer Cmts.User) hide
(effects (font (size 0.2 0.2) (thickness 0.02)))
)
(fp_text value Via (at 0 -0.9) (layer F.SilkS) hide
(effects (font (size 0.3 0.3) (thickness 0.03)))
)
*(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers .Cu))
)

You can now put tracks to this without DRC violations and when you make a buried via with bigger sized annular rings it will work…
So all that would be left to do for some programmer is to put in an option to tell the buried via method to not to create annular rings between the layers the buried via is supposed to connect.
Then you’d be done, as you’ll have at least 2 tracks going to the via at different levels, otherwise you don’t need any bigger sized annular rings anyway, right?
Or do I miss a case here?

800Ă—422 80.6 KB

1 Like
9

Thank you very much for your hints! We will try it out.

I have talked now to the PCB manufacturer and got some news. They told me that we might simplify the things a bit, because they will remove annular rings from vias in inner layers anyway - if there is no track connected to it. They call them “Non Functional Pads”. Thy will do it with their CAM tools on gerber basis.

But even if thy do so, one problem remains: In our gerber files, the surrounding copper area will not be filled near enough to the via in inner layers (because the filling algorithm will see the annular ring there).

Maybe this problem can be solved without a padstack editor. In our case, it would be nice to have an option, removing all annular rings from inner layers, when they are not connected to a track.

I will keep you informed and post our results here.

10

if you don’t want annular rings on non connected to layer inner pads, you can do like that:

a module with pads only on tracked/connected-to-layer pads

(module ann_via (layer Front) (tedit 561F5CF9) (tstamp 561F9B2E)
(at 126.45898 136.2202)
(fp_text reference AV100 (at 0 0.9) (layer Cmts.User) hide
(effects (font (size 0.2 0.2) (thickness 0.02)))
)
(fp_text value Via (at 0 -0.9) (layer F.SilkS) hide
(effects (font (size 0.3 0.3) (thickness 0.03)))
)
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers Front)
(net 4 N-000002))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers Back)
(net 4 N-000002))
(pad 1 thru_hole circle (at 0 0) (size 0.7 0.7) (drill 0.4) (layers In4.Cu)
(net 4 N-000002))
)

that will produce only annular on tracked pads, but with DRC violations

787Ă—1036 40.2 KB

that will reduce also the filling problem

750Ă—844 27.2 KB

from the picture you can see that internal fill zone (layer without annular) is closer to drill than the top fill zone where there is the annular

2 Likes
11

interesting for me that on layers where there are no pads it keeps zones from filling up to the hole. Fascinating.

12

Well, if it filled the zone all the way, there would be a pad again, a large one. Can’t have that if the hole is plated. Even for unplated holes it would be pushing one’s luck. Can’t guarantee that the inside surface of the hole is 100% free of copper, especially if the drill is a bit dull and starts smearing the stuff all over the place.

The case shown in the image above seems a bit excessive though. I guess it would be sufficient to keep the zone away from the hole by oh say 0.5x drill diameter, maybe less if the drill registration is optimal.

13

I’m happy about your support in this forum - thanks to you all!

Yesterday we’ve checked the proposal from maui, using pads instead of vias. This would solve our problem. We will see if we can define those pads within the BGA footprint, allowing us to reuse those settings for other projects.

Of course, all of this is a workaround, and a padstack editor would give us a much more elegant solution.

But in our case - we would also be happy with an option for the gerber export dialog like “Remove Non Functional Pads from Inner Layers”. This is something the PCB manufacturer will do anyway. It would be necessary that the released area of the annular ring will be used by the surrounding copper zone (respecting the clearance area around the drill hole). This option would also be useful if the padstack editor is completed one day.
For me it seems that an option like this is no witchcraft. I could ask one of our C++ experts if he is brave enough to try it.If this works we could contribute the code.
But what is you opinion? Would this option be useful for you, too? Would it be a an easy job to implement it? Or do you see any pifalls?

3 Likes
14

I think that would be a good idea…
please have a look at
https://kicad.org/contribute/developers/

a padstack editor would be a useful thing
you can ask at the developers mailing list if someone has already started something (but I don’t think so) and if there are some constrains to follow…
also the chat is available…

looking for your feedback :smile:
M

15

I like it. I don’t do 4 or more layer boards yet, but it would be definitely helpful if I ever came across BGAs where every little space one can get for routing underneath is worth it’s space in gold :wink:

1 Like
16

Any more thoughts about this? I was referred to this topic, having had a related problem wanting special pads on the solder side only of through hole components, especially circular connectors and would find a padstack editor very useful for even two layer boards.

1 Like
17

Padstack editor is nice, but it does not solve this problem.

Removing unconnected internal layers annular ring is an optional processing step before tapeout to fab.

Needs to be an option to remove.

But you can normally also ask your pcb manufacturer to remove them in theirs cam station.

The good ones will do that, and even remind you when you forget.

Capacitance is what’s to be reduced.
Not resistance as mentioned earlier.

1 Like
18

And thermal load affecting soldering

19

Hello guys,

just wanted to check is this problem solved. I have been doing 6 layer board and I need my ground plane underneath MCU and RAM not so drill riddled.

818Ă—632 16.3 KB

Its been almost a year so I hope there is solution for this, at least can anyone explain me where do you enter those code examples.
( and question aside, how come my 3D viewer doesnt show me layers like yours
735Ă—456 3.03 KB

1918Ă—934 90.1 KB
)
Tnx

1 Like
20

you need to select the option to render as technical mode (not realistic mode)

1 Like