This has been discussed over the years and Kicad now offers a couple options for setting the Annular Ring size (Connected layers only, Start/End/Connected) but today I’m submitting a board that could need different size Inner Annular Rings (IAR) on the inner layers. In my case, this could significantly reduce the cost per PCB ordered.
I have a BGA chip that needs lots of VIA’s. It’s 14x14 balls. Each ball is 0.4mm and the space between balls are 0.8mm. Smallest final hole at my vendor is 0.15mm so I use via’s with a 0.45mm Diameter. The Via’s cannot be larger than 0.45mm for isolation purposes. If I could change the size of the Annular Rings to 0.5mm on the inner layers, this would reduce the price of each board with many dollars since the smallest filnal would be 0.05mm bigger and that would make the board poolable (with Eurocircuits in my case).
OP on the thread from 2015 has several good suggestions and a “padstack editor” is obviously ideal. I’ve searched the forums and web for this, but cannot find anything new. I understand that this may be a niche feature, but is Padstack Editor a feature being worked on? And is editing files manually still the solution as it was in 2015? Thanks!
Screenshot of existing options and how my BGA looks at the moment
There’s no off-the-shelf solution. I haven’t tried, but I would say it would be possible with scripting and custom rules.
Because the inner layer annular rings are larger, you should first write a rule for larger clearance for vias in inner layers. That way you would have enough space for them in all situations.
Then comes the tricky part. KiCad actually accepts and recognizes SMD pads in inner layers if I remember correctly. You would need to add an inner SMD pad to each inner layer for each via. That would be done with a python script and would be the last step after the locations of all vias have been fixed.
In the meantime, if you want to do it manually, you could create a single hole footprint with a THT pad with small annular ring, and put SMT pads at the top & bottom. You will also have to add these footprints to the nets.
That would be the easy way to make it if the outer layer annular rings would be larger. But I don’t think it works when the inner layers should be larger. The THT pad must have the smaller diameter, and the larger diameter must be done with SMD pads.
Sure. Those are all minimum values. Using the absolute minimums possible would produce astronomical prices and absolute no chance for pooling of a defined impedance PCB
The settings I use are specifically to be the smallest possible and still be poolable. If your boards don’t go into a pool with other boards, they’ll increase 2-3 times in price (or more) so I specifically stay within those limits. Eurocircuits have a rather complex table explaining what will increase your price Classification - Eurocircuits
It sounded really odd when the customer rep told me that if the inner layers could be just a little bigger, I’d get within their IAR requirements for standard pooling. For now, I went for the slightly more expensive option of 0.1mm “Smallest final hole”. That’s $5 ekstra per board but if I could make the internal via 0.05mm bigger than the outer layers, I could save that too. Not all that important now that I’m prototyping, but once the customer starts making thousands of boards it’s measurable.
