Is there a way to set pad clearance (for copper) different than track clearance (for copper)? Under the Design Rules Editor, Net Classes Tab there is a Clearance field. In the Global Design Rules tab there is table for custom via sizes but it only has pad size and drill size. No field for pad clearance. Under the Dimensions pulldown there is a tab for Local Clearance and Setting but this appears to be for mask and past clearances. I want to set the copper clearances differently for pads than for tracks. Thanks!
right click the footprint, properties, …
(You beat me to it!)
You can also set the clearance on a pad-by-pad basis, either in the footprint editor or after placing a footprint on the board. Go to the “Pad Properties” dialog (“E” is the shortcut key) and select the “Local Clearance and Settings” tab.
p.s. After changing pad clearance using any of these methods, remember to re-pour the copper fill areas.
Now that you mention it…
I think if you want to change them all in one swoop you can use the Dimensions > Pads > Local Clearance and Settings tab… not working (tested in BZR6971)
Thanks for the quick replies. I realize I typed the wrong thing. What I wanted to know was how to set the pads clearance for Vias vs copper clearance for tracks. Are the settings you mentioned the same for via pads? I really don’t want to have to set them all individually. Do the settings under Dimensions > Pads > Local Clearance and Settings tab also effect via pads? Or is there a separate setting for those?
Hm… I always thought that the menu in my last screenshot would be the global setting, but this doesn’t seem to work.
Just tested this the last 5 minutes and there is no global pad clearance setting anywhere to be found.
One can adjust the single pads and the footprint, but not all footprints on a layout in one swoop.
As for the vias… there is not even a setting. They are linked to the net/track setting that you already found.
Ouch. Ok. My vendor wants 20 mil spacing around via pads that do not have connections. So if I understand this correctly, this means if I want the DRC to catch this, I must use 20 mil clearance for my all my copper tracks?
From my POV, yes.
But I’m with KiCAD for ~1 year now, others might know more or workarounds… maybe they chime in if that’s the case.
Btw, via pads that don’t have connections?
What use case have those?
Also, KiCAD does remove the net from vias if they are ‘loose’ upon reloading the layout…
PS: a workaround would be to use PTH footprints with the correct clearance set and use those as vias… the schematic will get a little bit complicated though.
Is this a test probing requirement perhaps?
I am working with 4 layers for a rigid-flex design. According to the 3D viewer (and verified by viewing in the Gerber layers) when you place a through via (top to bottom), Kicad places “pads” or rings around the via at all the layers.
The importance is due to the rigid-flex design construction and trying to keep the cost down. The construction is a ‘standard’ two layer FR4 rigid, adhered to a ‘standard’ two layer flex. (See image below)
The reasoning is, if I use only through vias (as opposed to blind/or buried vias), they will only need to drill and plate once, after assembling the rigid to the flex. What this means is that my formally blind or buried vias now must have clearance around the copper via pads on the layers where I don’t want an electrical connection. I am told the alternative is significantly more expensive.
This restricts my laying the tracks a little more but I’m hoping worth the savings. Hopefully this clarifies why I want to set the via pad copper clearance different from the copper track clearance? I am hoping to use this work-around: Use larger via pads throughout as I lay new tracks. When finished with the board go back and change all the vias to smaller pads that will then give the proper clearance… perhaps by manually editing the kicad_pcb file? Alternately, I could use the correct or desired final via size, user larger tracks throughout the design. When finished with the board go back and change all the track sizes to a smaller size that would give the proper clearance. Somehow, the latter seams like more work. My goal is to use the DRC to check for less than 20 mil copper clearance. Any thoughts?
That should work.
If you do the zone fills & track laying with the large vias and before you plot the gerbers you just change the via copper pad size and you should be good.
I like it.
UPDATE: Miscommunication with vendor on required clearance. I won’t go into all the details of the confusion but wanted to upate that the required clearance is 5 mil around the 18 mil copper via pad. They had different tolerances for inner via clearance but since my inner layers are not very crowded, I choose to just stick to the 5 mil for all layers.
Besides, it doesn’t appear like Kicad natively allows you to set the inner pad size, although there are some solutions discussed in this other thread :
A picture is worth 1000 words. Vendors who take the time to create and publish sketches such as in your post give me more confidence, and receive greater respect, than those who try to describe such requirements in words alone.
It has been almost half a century since a college instructor told me that I’d spend an entire engineering career making drawings. I dismissed the statement as hyperbole, since my major was electronics engineering, and I was aware of exciting and impressive things happening in word processing and automated publishing. However, I must now grudgingly acknowledge that he was correct.
JLCPCB has a 3.5mil spacing design rule track to track, but a 5 mil spacing track to via. I read this thread from long ago, best suggestion ( IMHO ) is to change all vias to larger size,re-pour, fix errors, then globally reduce vias to their final size.
Does Kicad still not support different spacing ruled for via to track ( compared with track to track )?
If not, are there any better suggestions on how to work around?
( My board is already laid out, 1600 components and 0.9mm spacings everywhere! )
3.5mil spacing is super tiny. Do you need to design to clearances that small? General rule of thumb is to not design right up to a manufacturer’s minimums unless necessary. Can you get away with a global copper to copper spacing of 6mil or larger? Then you don’t have to worry about different clearances for different types of features. Hmm… you seem to have answered that already (unless I did my conversion wrong or you made a typo). You say “0.9mm spacings everywhere”. 0.9mm is 35.4mil… acres of space.
Sorry, typo…0.09 mm spacings everywhere. It’s a VERY busy board…
If KiCad cannot support different clearance rules from track to track versus track to Via, does anyone have any suggestions for a suitable DRC tool I can run on my data that DOES support setting different spacing rules?
I am going ahead and increasing my via size and then correcting the ( 1100 ) DRC errors…but once I am done, all I can do is change all the vias back to the small size again …and ship the data to JLCPCB and hope for the best…I’d rather be able to DRC check in a similar way to the way that JLCPCB will do: with seperate rules…before I ship Gerber…
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