Prevent via pads on all layers?

I have a four layer board with plated through vias. What I expect is if the net is unused on a given layer then the hole should not have a pad around it, but a simple test with a one resistor layout shows pads around the drill holes on every layer when I view the exported gerbers.

This image illustrates what I am after. A: Is what I’m trying to get, B: is what I’m getting. My trace for the example hole only goes to the top and bottom layers so I don’t need the pads on the inner layers


Likewise if I have a trace from the top to the first inner layer then I would not want pads on the second and bottom layers. Am I missing some important aspect of how vias are manufactured again?

For my design I need every micrometer I can get so am hoping if I can get rid of those inner pads I can increase the clearance on the inner layers.


Just thought I would attach the test project. (8.6 KB)

And an image from the 3D viewer that is the same as the gerbers.


Yeah that’s the answer thanks.

But frustrating that KiCad still doesn’t deal with high density connectors and BGAs easily.
This will have to be v6 now.

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