Optimizing Annular Rings of Vias in Inner Layers

[Indir_Okanovic]

@kammutierspule

you need to select the option to render as technical mode (not realistic mode)

Thanks man! Now its so obvious.

[Indir_Okanovic]

I did some research and even with 0.4 mm via pad and 0.2 mm via drill i still have the same problem, there is just to much clearance between via annular ring and nearest copper ( I calculated that default setting in KiCad is 0.2 mm clearance ). And there is no way i can route properly without losing my ground plane.
For my design ( BGA packaging with 0.8 pall pitch ) I need at least 0.1 mm clearance.

[Rene_Poschl]

You can change the clearance settings in within the design rules.
Ground plane clearance is set within the plane settings itself. (Don’t forget the copper min width.)