Antipad in inner layers / inner restring specification

[MisterHW]

Some designs would greatly benefit from inner layer antipads being defined by specific design rules (the current ones are general for all layers) for

• clearance to (non-)plated through holes,
• clearance to orphaned nets representing the via barrel or
• per-layer restring width.

A detailed discussion seems to have started in 2015,

Optimizing Annular Rings of Vias in Inner Layers

You can change the clearance settings in within the design rules. Ground plane clearance is set within the plane settings itself. (Don’t forget the copper min width.)

but as of today it seems the last mention (Dec 2019) is "doesn’t work, but you can ignore the 3 DRC errors per pad and specify smd + thru_hole):

Anti-pads in inner layers?

Hi, Either I’m misunderstanding something or I can’t find a way to accomplish the feature shown in the image below at https://www.polarinstruments.com/support/si/images/ap8178_1a.jpg: [image] KiCad seems to give me no option other than creating a pad in the inner layer, then apply some clearance around that pad. (that’s what I see both in the pcbnew view and in the Gerbers) Is it possible to specify a via (or a pad in a footprint) with this characteristic? If not directly, is there any “h…

Since I don’t have a large BOM in the project in question, the option seems to be to create modified copies of footprints and using them until inner layer restring specifications or design rules have been implemented.

However! It turns out that in particular smd oval is not calculated correctly, leading to a smaller pad size being used for antipad shape calculation on the front and back layers.
Just documenting this here to give it a place and to warn others looking for inner restring issues.

Example:

  (pad 1 smd roundrect (at -5.45 0) (size 2.2 4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.3))
  (pad 1 smd roundrect (at -5.45 0) (size 2.2 4) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.3))
  (pad 1 thru_hole circle (at -5.45 0) (size 1.8 1.8) (drill 1.5) (layers *.Cu *.Mask))

I tested the assumption whether just the first of a set of overlapping pads is used to calculate the antipad (top left and top right), which turned out to be false. At the bottom it is shown that only smd roundrect produces the appropriate antipad shape in the outer layers.

[MisterHW]

As an example, here’s a commercial VFD power stage board showing smaller inner antipad diameter hinting at layer-dependent clearance for the same set of nets or nuanced restring configuration.