Anti-pads in inner layers?

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1

Hi,

Either I’m misunderstanding something or I can’t find a way to accomplish the feature shown in the image below at https://www.polarinstruments.com/support/si/images/ap8178_1a.jpg:

image

KiCad seems to give me no option other than creating a pad in the inner layer, then apply some clearance around that pad. (that’s what I see both in the pcbnew view and in the Gerbers)

Is it possible to specify a via (or a pad in a footprint) with this characteristic? If not directly, is there any “hack” that would work and be convenient and would not make PCB manufacturers mad at me?

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2

Through holes (including vias) in KiCad have the same copper ring and clearance on all layers. There is no way to remove the copper ring on an inner layer at this point in time. A more complex pad stackup handler is planned for version 6 (to be expected in a year or two.)

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3

Your question is: Is the hole metalization possible if there is no contact to it at inner layer.
I don’t know the answer but I see it at least problematic.

4

Yes you do not need to contact a pad on every layer for it to be metallized. There does not even need to be a pad on every layer for it to be manufacturable. The only requirement is that the clearance to other features is large enough as you might otherwise create a short. This is definitely the case with the current KiCad implementation as the fact that you must have the same restring on all layers guarantees even more clearance than would be necessary just for the plated hole.

5

Thanks for letting me know. (and good t o hear for v6)

For the cases where one might absolutely require this (I’m not working on any such designs right now, but if-and-when…), would the following hack work:

(module via-with-antipad (layer F.Cu) (tedit 5DF7A297)
  (fp_text reference REF** (at 0 0.5) (layer F.SilkS) hide
    (effects (font (size 1 1) (thickness 0.15)))
  )
  (fp_text value via-with-antipad (at 0 -0.5) (layer F.Fab) hide
    (effects (font (size 1 1) (thickness 0.05)))
  )
  (pad 1 thru_hole circle (at 0 0) (size 0.5 0.5) (drill 0.5) (layers *.Cu))
  (pad 1 smd circle (at 0 0) (size 1 1) (layers F.Cu F.Mask))
  (pad 1 smd circle (at 0 0) (size 1 1) (layers B.Cu B.Mask))
)

KiCAD 5.1.5 seems to accept it and it seems to work, even though the DRC flags errors. But the Gerber files look exactly like I expect/want them to. What I’m not sure is whether that is legal Gerber that PCB manufacturers will be able to work with; e.g., defining a pad of 0.5mm diameter with a hole of 0.5mm diameter — does that lead to a valid Gerber construct?

6

Yes that would work. You are however limited to having large pads on the outside. There is not really a legitimate way to have some stranger pad stackup. And you also can only do it for full through holes not for example for vias that go through a part of the layer stack.

7

If you entertain illegitimate ways, you can add SMD pads on all layers with arbitrary pad size and clearance. And if you want to get extra silly, a bit of Python could pull out vias of a certain type and swap in a custom footprint.

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