Custom Design rules Examples

KiCad has the ability to create custom design rules for DRC that modify how clearances are calculated and applied.

The formal documenation for these custom design rules is on:

This FAQ article is an attempt / start to collect examples of such rules.

  1. A short description on what the goal of the rule is, preferably with a link to a picture already on this forum (just copy a link from the original and post it here. No need to copy the whole picture. This forum software understands).
  2. The actual text of the rule itself.
  3. A direct link to the thread the rule was posted.
  4. More? (I’m no expert on these rules myself).

There are also examples of rules in: PCB Editor / File / Board Setup / Design Rules / Custom Rules / Syntax help which is the small inconspicuous light blue text in the upper right corner:


Keeping a clearance between a zone and tracks in that zone belonging to the same net

The Rule:

(rule samenet
(condition "A.Type == 'Zone' && A.NetName == B.NetName")
(constraint physical_clearance (min 0.2mm))

Also, “Mic” posted “this works for me”

(rule gnd_top_separation
(layer "F.Cu")
(condition "A.Type == 'Zone' && A.NetName == 'GND' && B.NetName == 'GND'")
(constraint physical_clearance(min 0.25mm))

Forum link:


Check for minimum line width on a silk screen layer

(rule "Minimum silkscreen line width"
	(severity warning)
	(constraint assertion "A.Line_Width >= 0.15mm")
	(condition "A.Layer == '?.Silkscreen' && A.Type != 'text'"))

Forum topic
Note: This link also has lots of other hints about rules syntax.


Creating a big clearance between net classes in a “High voltage” section and the rest of the PCB

The trick here is to create netclass names starting with a recognizable string (“HV”) and using that in the rules.
Rules are also applied in order, and the thread discusses some of the consequences of that.

(version 1)

(rule "LoW cLeArAnce BeTWeen neTS of THe SAme HV potential"
	(constraint clearance (min 0.2mm))
	(condition " A.NetClass == B.NetClass && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen neTS of dIfferenT HV potentials"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass != B.NetClass && A.NetClass == 'HV*'  && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen LV And HV neTS"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass == 'HV*' && B.NetClass != 'HV*'" ))

(rule "Reduced cLeArAnce for HV PoTenTIALS cLoSe To comPonenTS"
	(constraint clearance (min 1mm))
	(condition " A.insideCourtyard('*') && A.NetClass == 'HV*' "))

Forum topic


Minimum width of a zone

(rule absolute_min_zone_width
   (constraint assertion "A.Minimum_Width >= x.xmm")
   (condition "A.Type == 'Zone'"))

Although personally I would just draw a copper track (with a certain width) through the zone to ensure a certain width as I also mentioned in that thread. But to each his own solution.


Clearance between via’s and tracks of the same net.

(rule "via_not_in_pad"
    (condition "A.Type == 'via' && B.Type == 'pad'")
    (constraint physical_hole_clearance (min 0.01in))