Custom Design rules Examples

[paulvdh]

KiCad has the ability to create custom design rules for DRC that modify how clearances are calculated and applied.

The formal documenation for these custom design rules is on:

PCB Editor | 7.0 | English | Documentation | KiCad

This FAQ article is an attempt / start to collect examples of such rules.

1. A short description on what the goal of the rule is, preferably with a link to a picture already on this forum (just copy a link from the original and post it here. No need to copy the whole picture. This forum software understands).
2. The actual text of the rule itself.
3. A direct link to the thread the rule was posted.
4. More? (I’m no expert on these rules myself).

There are also examples of rules in: PCB Editor / File / Board Setup / Design Rules / Custom Rules / Syntax help which is the small inconspicuous light blue text in the upper right corner:

[paulvdh]

Keeping a clearance between a zone and tracks in that zone belonging to the same net

The Rule:

(rule samenet
(condition "A.Type == 'Zone' && A.NetName == B.NetName")
(constraint physical_clearance (min 0.2mm))
)

Also, “Mic” posted “this works for me”

(rule gnd_top_separation
(layer "F.Cu")
(condition "A.Type == 'Zone' && A.NetName == 'GND' && B.NetName == 'GND'")
(constraint physical_clearance(min 0.25mm))
)

Forum link:

(Zones) Don't pour over same net objects

I’m probably the 10000th user comparing Altium and KiCad, sorry for that. Altium has this option for Polygon Pours called “Don’t pour over same net objects”, which is something I like to use to separate the ground plane on the top layer from all Ground-going signals to inner layers. What happens is that none of the ground plane will go over any tracks. The only thing in KiCad I can find is the option to not pour over any pads, which is only half the battle. How can I achieve the same thing? …

[paulvdh]

Check for minimum line width on a silk screen layer

(rule "Minimum silkscreen line width"
	(severity warning)
	(constraint assertion "A.Line_Width >= 0.15mm")
	(condition "A.Layer == '?.Silkscreen' && A.Type != 'text'"))

Forum topic
Note: This link also has lots of other hints about rules syntax.

A few questions about Custom Rules syntax

Yes, I’ve been using assert for years with embedded devices (which for some reason is not widely used) and not only during the development stage but leaving the asserts even when the device is finished. Here is how that could look like in case someone is interested: my_dbg.h #ifndef my_dbg_header #define my_dbg_header #include <stdlib.h> #include "lcd.h" #include "pisanje.h" #define DEBUG 0 // za #if DEBUG //#define NDEBUG // za assert() #define __ASSERT_USE_STDERR // da bi se pozvalo …

[paulvdh]

Creating a big clearance between net classes in a “High voltage” section and the rest of the PCB

The trick here is to create netclass names starting with a recognizable string (“HV”) and using that in the rules.
Rules are also applied in order, and the thread discusses some of the consequences of that.

(version 1)

(rule "LoW cLeArAnce BeTWeen neTS of THe SAme HV potential"
	(constraint clearance (min 0.2mm))
	(condition " A.NetClass == B.NetClass && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen neTS of dIfferenT HV potentials"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass != B.NetClass && A.NetClass == 'HV*'  && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen LV And HV neTS"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass == 'HV*' && B.NetClass != 'HV*'" ))

(rule "Reduced cLeArAnce for HV PoTenTIALS cLoSe To comPonenTS"
	(constraint clearance (min 1mm))
	(condition " A.insideCourtyard('*') && A.NetClass == 'HV*' "))

Forum topic

KiCad 6.0 custom design rules for HV clearances

One of the features I have been looking forward to the most in KiCad 6.0 is the ability to specify design rules that apply only under certain circumstances or between certain net classes. My simplified use case is half bridge circuit consisting of 2 HV rails, HV+ and HV-, a phase output that could be at HV+, HV- or floating potential depending on the MOSFET states. The low voltage control system is totally isolated from the HV system via an isolation barrier within the gate driver ICs and the i…

[paulvdh]

Minimum width of a zone

(rule absolute_min_zone_width
   (constraint assertion "A.Minimum_Width >= x.xmm")
   (condition "A.Type == 'Zone'"))

How to use the "Min_Width" Zone Property in Custom Rules?

Although it appears to have been renamed in the code to Minimum_Width, and the docs call it Min_Width. How can I make use of this? It looks like this can’t be used as a constraint, but only as a condition, which doesn’t really make sense to me. My end goal is to have some DRC to check minimum zone width. Say I have net classes for checking all my minimum track thicknesses, and one track is too thin. If I replace it with a zone with the same dimensions, the DRC error will disappear, but the prob…

Although personally I would just draw a copper track (with a certain width) through the zone to ensure a certain width as I also mentioned in that thread. But to each his own solution.

[paulvdh]

Clearance between via’s and tracks of the same net.

(rule "via_not_in_pad"
    (condition "A.Type == 'via' && B.Type == 'pad'")
    (constraint physical_hole_clearance (min 0.01in))
    )

Via to pad same net clearance constraint?

Is there a way to create a custom design rule to check for vias getting too close to pads of the same net? I have looked everywhere and there doesn’t appear to be one. I don’t know about you all but I’m not comfortable with trusting my vigilance to see if a via gets too close to a pad such that I have to designate to the manufacturer that that via is “via-in-pad” and thereby increase the cost of my board. I avoid via-in-pad unless it’s necessary for thermal or high-density reasons. The probl…