Clearance between different net classes?

Layout
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A barrier is exactly what you describe. Two groups of nets that can be close to their own kind, but keep a large distance from the other.

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Ah, OK. I didn’t needed that granularity yet, thus I wouldn’t know about that limitation. Sorry.

@davidsrsb was probably talking about using Keep-Out zones between HV/LV tracks for routing purposes/zone filling - but sounds like a lot of manual work and won’t help you when putting down tracks manually.

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For example, any circuitry with a galvanic connection to the power mains (e.g., the switch, fuse and primary circuit of a power transformer) must have a certain isolation distance from the secondary circuit of the transformer.

Dale

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@dchisholm Yes, this is the sort of thing that should be handled by a design rule and is already handled more-or-less well in KiCad.

It sounds like the functionality I’m looking for doesn’t exist in KiCad (this is what I expected, since I couldn’t find it). Is there a way to put in a suggestion for this feature? I’m not really software-savvy enough to write it myself, but I know it would make KiCad more friendly for the power electronics community.

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I have also been looking for the requested feature due to an actual project, and did not get it around (version 5.0 rc2). The suggestion to do it using a keepout zone is however usable, because the main problem is just a desired copper pour behaviour.

However, net class relationships/groups would be “foolproof” because of design rule checking upon routing&placement.
I know of such a feature with Altium Designer, but their solution requires a bit too much attention not to overlook clearance rules. A simpler approach would be the introduction of a sort of net group name. The current net class assignment could serve for this: A parameter that specifies a bigger clearance towards ALL other net classes would do the job. Better would be an extra parameter containing an exclusion list, so you could use more than one net class on the imagined high voltage plane.

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This is an old thread but I came up with a work around that I think works better and is more convenient than a keepout zone - it could be useful to others. . I created a third net class with a clearance of one half the desired class-to-class clearance. Then I drew a trace belonging to this third class between the two circuit areas. You can also add another net class for reduced clearance on interior layers.
It is not perfect; it only indirectly checks for the desired clearance. It never misses a violation but sometimes there are false positives. To fix a false positive you simply move the barrier trace to be half way between the two nearest points. Of course you have to delete the barrier traces before generating gerbers.

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Because this was raised it’s appropriate to tell that v6.0 will have enhanced DRC rule system which works for these kinds of cases. See Need some guinea pigs for a rule-based DRC <<PROTOTYPE>>.

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Do we have a way now th set the clearance between different net classes?

Let’s say that I have a design with 16 net classes and I would like to have the default rules within every net class but I would like to set a certain clearance (the same) between them. There is a simple DRC rule that can state that?

Thanks
A

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Yes.
From the Schematic manual:
https://docs.kicad.org/7.0/en/eeschema/eeschema.html#schematic-netclasses

Then follow the included link to the PCB documentation.

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I do not know much about these custom design rules, but questions about them keep popping up an I have been collecting examples of working rules. You can find them in the link below. And you can of course also read the manual :slight_smile:

When you wrote:

My first thought was “something similar to the ERC Pin Conflicts Map”:

image
image1060Ă—538 77.1 KB

But then, of course with clearances between the net classes instead of sorts of connections between pins. But I am not sure how useful that would be.

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Once you follow the link from Schematic netclasses to the PCB documentation, you find this:

ksnip_20231207-111843
ksnip_20231207-111843876Ă—693 154 KB

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@craftyjon

Let me rephrase: let’s say the default clearance is 0.3mm. Now I have defined n1 - n16 net classes.

What is the custom script to define the clearance between each net classes (n1 relative to n2, n3, … n16, n2 relative to n3, n4, … n16, etc…) being 2mm? This means within a net class the clearance is 0.3 and between net classes the insulation is 2mm?

I wasn’t able to figure out if it’s possible to set such rule in KiCAD V7.

Thanks,
Andrei

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Should be something like this. Repeat for your other combinations. If you really care about all combinations you’re going to have to do a lot of rules; usually the matrix is more sparse than that and you can do one or two general rules with some specific overrides.

(rule clearance_netclass1_to_netclass2
	(condition "A.NetClass == 'netclass1' && B.NetClass == 'netclass2'")
	(constraint clearance (min 1mm)))

I haven’t tested this, hopefully no typos.

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Here’s an example that does what you asked for:
netclass_rules_example.zip (5.2 KB)

(rule different_netclass_clearance
  (condition "A.NetClass != 'Default' && A.NetClass != B.NetClass")
  (constraint clearance (min 2mm)))
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@craftyjon
Thanks Jon. Works perfectly!

The syntax does support wildcards? eg: N1 … N22, N* or N?

Best Regards,
Andrei

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Yup. N* should work for you.

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Thanks Jon.

So an independent graphical DRC rule compiler (where you set clearances, conditions, etc) that optimize the checking steps would be possible… :slight_smile:

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@craftyjon

in my opinion the DRC rules need a compiler in order to get optimized… KiCAD routing becomes very slow when a big set of rules is defined, so we should avoid rules overlapping…

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