I design circuits with multiple voltage domains, and therefore require different clearances between domains. For example, there might be some ground-referenced logic (gnd+5V) and some other logic that sits 400 V above ground (400V + 5V). Obviously a 400V bus should have large clearance to gnd, but that kind of clearance is both unnecessary and disruptive for the logic whose voltages are never more than a few volts away from 400.
Example in KiCad: I have two nets, GND and BUS (400V), which I put into two net classes, LV and HV. I set the clearance on HV to be very large (e.g. 40 mils), while the clearance for LV is only 10 mils. Now consider that I have a VCC at 5V, which belongs to the LV class. I also have a VCC+, which is 405 V above ground. VCC+ should have large clearance to GND, but small clearance to BUS. But as it stands, if I put VCC+ in the HV class then it will have large clearance to everything; if I put it in the LV class, it could potentially come too close to GND or signals close to GND.
In other software, I could say “clearance between LV and HV is nets is 40 mils; clearance between HV nets and other HV nets is 10 mils” which solves the problem in a very logically consistent way.
Is this possible in KiCad? If not, is there a place I can suggest it?
@Joan_Sparky Yes, the design rules are just the place for this. The problem is that the rules you can set for a certain net class apply to its separation from every other net. So if I put Net A in a class with a design rule: “clearance = 0.2”, then KiCad will enforce that everything be at least 0.2mm away from Net A. However, I want to be able to say “enforce that nets from class 1 must be 0.5mm away from nets of class 2, but nets of class 2 can be as close as 0.1mm away from other nets in class 2.” And every permutation of that (see https://zavax.files.wordpress.com/2013/12/ad_design_rule_hole_copper.jpg for the way altium does this. You set up a rule for clearance between two things. Those things can be as all-inclusive as “everything” or as specific as “net A must be some clearance from net B.”)
@davidsrsb I’m not sure what you mean by a safety barrier. I’m simply talking about defining clearance between nets, and being able to do so with more granularity.
Ah, OK. I didn’t needed that granularity yet, thus I wouldn’t know about that limitation. Sorry.
@davidsrsb was probably talking about using Keep-Out zones between HV/LV tracks for routing purposes/zone filling - but sounds like a lot of manual work and won’t help you when putting down tracks manually.
For example, any circuitry with a galvanic connection to the power mains (e.g., the switch, fuse and primary circuit of a power transformer) must have a certain isolation distance from the secondary circuit of the transformer.
@dchisholm Yes, this is the sort of thing that should be handled by a design rule and is already handled more-or-less well in KiCad.
It sounds like the functionality I’m looking for doesn’t exist in KiCad (this is what I expected, since I couldn’t find it). Is there a way to put in a suggestion for this feature? I’m not really software-savvy enough to write it myself, but I know it would make KiCad more friendly for the power electronics community.
I have also been looking for the requested feature due to an actual project, and did not get it around (version 5.0 rc2). The suggestion to do it using a keepout zone is however usable, because the main problem is just a desired copper pour behaviour.
However, net class relationships/groups would be “foolproof” because of design rule checking upon routing&placement.
I know of such a feature with Altium Designer, but their solution requires a bit too much attention not to overlook clearance rules. A simpler approach would be the introduction of a sort of net group name. The current net class assignment could serve for this: A parameter that specifies a bigger clearance towards ALL other net classes would do the job. Better would be an extra parameter containing an exclusion list, so you could use more than one net class on the imagined high voltage plane.
This is an old thread but I came up with a work around that I think works better and is more convenient than a keepout zone - it could be useful to others. . I created a third net class with a clearance of one half the desired class-to-class clearance. Then I drew a trace belonging to this third class between the two circuit areas. You can also add another net class for reduced clearance on interior layers.
It is not perfect; it only indirectly checks for the desired clearance. It never misses a violation but sometimes there are false positives. To fix a false positive you simply move the barrier trace to be half way between the two nearest points. Of course you have to delete the barrier traces before generating gerbers.
Do we have a way now th set the clearance between different net classes?
Let’s say that I have a design with 16 net classes and I would like to have the default rules within every net class but I would like to set a certain clearance (the same) between them. There is a simple DRC rule that can state that?
I do not know much about these custom design rules, but questions about them keep popping up an I have been collecting examples of working rules. You can find them in the link below. And you can of course also read the manual
When you wrote:
My first thought was “something similar to the ERC Pin Conflicts Map”:
Let me rephrase: let’s say the default clearance is 0.3mm. Now I have defined n1 - n16 net classes.
What is the custom script to define the clearance between each net classes (n1 relative to n2, n3, … n16, n2 relative to n3, n4, … n16, etc…) being 2mm? This means within a net class the clearance is 0.3 and between net classes the insulation is 2mm?
I wasn’t able to figure out if it’s possible to set such rule in KiCAD V7.
Should be something like this. Repeat for your other combinations. If you really care about all combinations you’re going to have to do a lot of rules; usually the matrix is more sparse than that and you can do one or two general rules with some specific overrides.
