Don’t worry @eelik, you won’t be able to please both of us. Tom’s development style and my development style are at opposing ends of the feedback axis. 
Most of the heavy lifting at present is being done by Tom, so favouring his approach right now probably makes most sense…
OK, thanks. All good as long as things to consider are kept in storage for later and aren’t forgotten.
I want a clearance inside the Area of 0.2mm only on the top layer. Any ideas how to formulate that condition?
I used the filled zone for that…
(rule HVSVN-GDVR
(layer outer)
(constraint clearance (min 0.2mm))
(condition “A.insideArea(‘tl’) && B.onLayer(‘TOP’)”)
)
I still get drc errors.
@JeffYoung @eelik @twl Ideas?
You probably don’t want to specify the layer info in the condition. Just use the outer layer clause:
(layer top) (or whatever your top layer name is).
(Even given that, it seems like it should have worked as you had it written…)
DRC and zone filling have now been moved over the the new rule-based engine. So the rule syntax can now be considered semi-frozen.
I’ve also added something that will help debugging your rules. See Inspect > Clearance Resolution… (You’ll need to select the two elements between which you want to inspect the clearance first.)
Hi everyone,
I’m trying to control the clearance between zone fills/tracks to the board edge and mounting holes (I need bigger clearance for mounting holes). Any idea how should I do that on the latest nightly?
Use Board Setup board edge clearance for non-mounting holes.
Write a DRC rule for mounting holes. You’ll probably want to detect them with a condition along the lines of:
A.Pad_Type == 'NPTH, mechanical'
Only trouble is, we forgot to expose Pad_Type so you’ll have to wait for the next nightly…
Only trouble is, we forgot to expose
Pad_Typeso you’ll have to wait for the next nightly…
It’s alright, I’ managed to get KiCad to build 
What about Zone to Board Edge clearance? Is it possible to define via the new DRC engine yet?
A.Type == 'Zone' && B.onLayer('Edge.Cuts')
Awesome, makes sense! Still trying to get my head around how the DRC system works.
We just changed the file naming system for the design rules files.
Previously the file was just called drc-rules but that was problematic because we don’t prevent more than one project in a directory. So, now the file is called <boardname>.kicad_dru
If you have an existing project that you’ve been testing with, you must manually rename the file (or else open your old file in a text editor and paste the contents into the design rules setup dialog in PcbNew)
New rule based DRC looks like it will be super handy for high voltage designs were we need different spacing between HV-HV traces and HV-LV traces.
Will these rules be enforced in real-time during routing, or checked post route during DRC?
It’s “real-time”. Of course it’s also checked afterwards.
Nice – it is hard to hold off on using 5.99 nightlies for production boards now
I know what you mean! I working on some 540V cards with multiple references and this would make my life so much easier
I’m trying to create a rule that allows me to highlight if the center distance between testpoints is less than 2.54mm.
Or since I use testpoints with a diameter of 1mm, the distance between the pads should be 1.54mm.
I have made several attempts but the DRC does not show me errors even if I approach your testpoints with each other with spacing between the pads less than 1.54mm.
I don’t know how to specify in the expression that a pad is part of a component in this case the testpoint.
An example:
(version 1)
(rule “Distance between test points”
(constraint clearance (min 2.54mm))
(condition “A.memberOf (‘TP29’) && B.memberOf (‘TP30’)”)
)
I had seen an example with padOf but this no longer exists in the last nightly.
Perhaps this type of rule is not yet possible to implement?
Thanks
NB:
I had opened a discussion where I also posted photos.
Clearance constraints are not checked when the net is the same, so that’s your first problem. Try using hole_clearance instead.
Second, memberOf() is only for groups, not footprints. So you’ll need to edit your test point footprint to add the pad to a group with a name. (But they can all be the same name, which will making writing the rule easier.)
Thanks,
I created the rule using the group name and it worked for all test points that are not on the same net.
For the test points on the same net what can I do? the pad is SMD and has no through holes.
I added “hole_clearance” but test points that break the rule are not detected.
I could use a graphics layer that has the same diameter as the pad.
I’ll do a test tomorrow.
Hmmm, yes. I didn’t notice that.
It’s a bit of a hack but you could put a silk ring in your TP and then do a silk_clearance rule.