Need some guinea pigs for a rule-based DRC <<PROTOTYPE>>

[craftyjon]

Important note for testers of the new system:

We just changed the file naming system for the design rules files.

Previously the file was just called drc-rules but that was problematic because we don’t prevent more than one project in a directory. So, now the file is called <boardname>.kicad_dru

If you have an existing project that you’ve been testing with, you must manually rename the file (or else open your old file in a text editor and paste the contents into the design rules setup dialog in PcbNew)

[Cliff_Brake]

New rule based DRC looks like it will be super handy for high voltage designs were we need different spacing between HV-HV traces and HV-LV traces.

Will these rules be enforced in real-time during routing, or checked post route during DRC?

[eelik]

It’s “real-time”. Of course it’s also checked afterwards.

[Cliff_Brake]

Nice – it is hard to hold off on using 5.99 nightlies for production boards now

[Naib]

I know what you mean! I working on some 540V cards with multiple references and this would make my life so much easier

[Fabio_De_Bernardi]

I’m trying to create a rule that allows me to highlight if the center distance between testpoints is less than 2.54mm.
Or since I use testpoints with a diameter of 1mm, the distance between the pads should be 1.54mm.
I have made several attempts but the DRC does not show me errors even if I approach your testpoints with each other with spacing between the pads less than 1.54mm.
I don’t know how to specify in the expression that a pad is part of a component in this case the testpoint.

An example:
(version 1)
(rule “Distance between test points”
(constraint clearance (min 2.54mm))
(condition “A.memberOf (‘TP29’) && B.memberOf (‘TP30’)”)
)

I had seen an example with padOf but this no longer exists in the last nightly.

Perhaps this type of rule is not yet possible to implement?

Thanks

NB:
I had opened a discussion where I also posted photos.

Rule to check distance between test points (5.99)

I wanted to create a rule to check distance between test point centers. I’m using 1mm diameter testpoint smd and they should be at least 2.54mm away from their centers. or 1.54mm between their edges. I tried some rules but to no avail. Can any of you who are familiar with the new system of rules help me? Thanks I attach photos: [Cattura] [Cattura1]

[JeffYoung]

Clearance constraints are not checked when the net is the same, so that’s your first problem. Try using hole_clearance instead.

Second, memberOf() is only for groups, not footprints. So you’ll need to edit your test point footprint to add the pad to a group with a name. (But they can all be the same name, which will making writing the rule easier.)

[Fabio_De_Bernardi]

Thanks,
I created the rule using the group name and it worked for all test points that are not on the same net.
For the test points on the same net what can I do? the pad is SMD and has no through holes.
I added “hole_clearance” but test points that break the rule are not detected.
I could use a graphics layer that has the same diameter as the pad.
I’ll do a test tomorrow.

[JeffYoung]

@Fabio_De_Bernardi

the pad is SMD and has no through holes

Hmmm, yes. I didn’t notice that.

It’s a bit of a hack but you could put a silk ring in your TP and then do a silk_clearance rule.

[Fabio_De_Bernardi]

I added a circle around the edge of the pad with both F. Silkscreen and courtyard.
I have tried with both silk_clearance and courtyard_clarance but the error is not encountered.
There are only warnings that silk covers the solder mask.

This is the rule I used:

(version 1)
(rule “Distance between test points”
(constraint silk_clearance (min 1.54mm))
(constraint clearance (min 1.54mm))
(condition “A.memberOf (‘TP1mm’) && B.memberOf (‘TP1mm’)”)
)

2020-12-23 14-35-30

[Fabio_De_Bernardi]

I tried this rule:

(version 1)
(rule “Distance between test points”
(constraint courtyard_clearance (min 1.54mm))
#COMMENT (constraint clearance (min 1.54mm))
(condition “A.memberOf (‘TP1mm’) && B.memberOf (‘TP1mm’)”)
)

But it finds no problem whether the testpoints are on the same network or on different networks.

[JeffYoung]

For the silk clearance test the circle (or whatever is on the silk layer) would also need to be a member of the group. Is that the case?

The courtyard test isn’t going to work because that just does a blind collision (rather than a clearance test). That probably needs to be fixed…

[Fabio_De_Bernardi]

Yes you were right, I hadn’t put the silk circle in the group.
He finds the violations but finds just as many among himself.

It would be better to have a courtyard test instead of silk as it can generate warnings with the solder mask.

[Naib]

Is there anyway to set clearance rules based upon soldermask?

900V at altitude requires 3.5mm with some form of coating (either paryleen or resist ) BUT uncoated pads would need 12-15mm. This could be screw terminals and thus would not be coated unless absolutely necessary due to the extra steps involved.

Likewise, does this take into consideration board cuts? slots are typically used to increase the creepage path (at the expense of mechanical robustness) while keep the board small

[Fabio_De_Bernardi]

I thought the problem of alerts between the same pad was due to the hidden text on the silk layer.
I changed the text to F.Fab but the problem remains.
I don’t understand what is detected.
Maybe because the diameter of the circle is smaller than the minimum distance?

I thought the problem of alerts between the same pad was due to the hidden text on the silk layer.
I changed the text to F.Fab but the problem remains.
I don’t understand what is detected.
Maybe because the diameter of the circle is smaller than the minimum distance?
Shouldn’t it test between its parts?
Since I used A. and B. no?

[JeffYoung]

It’s detecting the pad <-> silk collisions because the pad is also in the group.

You shouldn’t need the other rule anymore so try taking the pad out of the group.

[JeffYoung]

@Naib

Is there anyway to set clearance rules based upon soldermask?

900V at altitude requires 3.5mm with some form of coating (either paryleen or resist ) BUT uncoated pads would need 12-15mm. This could be screw terminals and thus would not be coated unless absolutely necessary due to the extra steps involved.

Likewise, does this take into consideration board cuts? slots are typically used to increase the creepage path (at the expense of mechanical robustness) while keep the board small

Creepage didn’t make it in to 6.0.

Add DRC checks for creepage (#5159) · Issues · KiCad / KiCad Source Code / kicad

(Ha! The bug report credits you with the idea.)

[Fabio_De_Bernardi]

Yes, I solved it by leaving only the silk circle in the group then I had to change the distances of the rule and the diameter of the circle otherwise there are problems with the soldermask which in my case is set in the global specifications to 0.05mm.
Thanks

[Naib]

yup its in this thread somewhere where I made the suggestion of edge cut creepage

HOWEVER, that was more of a z-axis consideration (in2 -> edge -> up -> edge -> in1 type thing). This is something I get very specific about.

what i describe here was more of an x-y around a slot. They are comparable creepage considerations, just different concerns.

Any idea about the difference between coated copper (resist or conformal) vs un-coated. This is one of the primary use-case considerations w.r.t. high-voltage.
I guess once there is some way of using net-ties (without the copper part) such that different parts of a net can have a different label while being treated the same would help as you could assign a label close to what would be the exposed pad. Right now the physical copper net-ties appear to be the workaround but they are well…

[JeffYoung]

If you want you can re-do it in the next couple of days using a courtyard_clearance rule. That won’t have the silk issues…

(couryard_clearance rules don’t work at all right now because they never got implemented.)

[Edit: bits are in. Should be in tonight’s nightlies.]