Custom Rules for Testpoint

Hello
I am really stuggling with the custom rules in KiCAD 9.
I tried to define a custom rule for the clearance between the testpoints. The state of the rule checker is No errors found. But the rule is not active and there is no error in the DRC.
I defined the custom rule:

(rule “Clearance Testpoints”
(constraint clearance (min 5.00mm))
(condition “A.Reference == ‘TP*’ && B.Reference == ‘TP*’”)
)

How I have to setup this rule? Do I have to activate the custom design rules some where else?

Regards
Céline

I am also not very proficient with the custom rules, but I have collected a few examples in:

Also, it’s mandatory to start with a (Version 1) statement.

Footprints don’t have clearance. You want apply the check to pads and use memberOfFootprint.

On this side PCB Editor | 9.0 | English | Documentation | KiCad is the example with the testpoints. How do I have to implement a correct rule?

For whole footprints you can use courtyard_clearance, as you can see in the example rule. For that both footprints must actually have a valid courtyard.

If you make your own courtyards…
Overlapping courtyards also generate DRC violations, so if you size them appropriately, there is no need for an extra custom rule.

Just my two cents:

The distance between TP is normally a problem for making the Test Nail Adapters (Drilling, adding the wires, use space for changeing the nails). Between the different Test Nails “Centers” we must have a spacing for example 2.54mm.

So the custom design rule for the TP in KiCad is not a problem of courtyard! It should be a rule for center to center. Of course if the TP is to bi in size we will have another problem.

Keeping all pins in a bed of nails on a 2.54mm grid makes it quite easy to use a piece of matrix / perf board to create the jig. I use KiCad in a DIY environment, and for all footprints for which it makes sense (headers, DIP IC’s, etc) I always place them on a 2.54mm grit. The atrocity that happened to “arduino” would never have slipped through my quality control. For quite a lot of things, modifications are easier if you incorporate the 2.54mm grid in your design.

1 Like

paulvdh

You miss understand me or I was not precise enough.

TP must not be on a general grid. TP can be placed any where on the PCB but must have a minimal distance (as ex. 2.54) to the nearest TP around.
A good custom design rule must describe that!

No, I did understand you perfectly well. However, in my opinion, by adding an additional constraint to put all testpoints on a 2.54mm grid, you have two benefits. You have a guaranteed distance between test points as you mentioned, and it also makes making one-off jigs easier, because you can make use of standard perf board.

If you only have a (rule with) a distance constraint of 2.54mm, then to make a bed of nails, you pretty much have to copy the project, and replace the testpoint footprints with pogo pin footprints, and then place the wiring. Adding a testpoint later is then error prone. If you keep all testpoints on a 2.54mm grid, then you can eyeball the location of additional testpoints, use a paper printout to verify locations etc. Locations are either perfect, or 2.54mm off.