Hello,
I am currently working on a six-layer PCB design that includes several BGA components. My PCB manufacturer, has specific requirements for BGA constraints, which are detailed in their guidelines: BGA Design Guidelines - PCB Layout Recommendations for BGA packages
I am seeking advice on how to incorporate the following specific parameters into my board:
BGA Pad Diameter: How do I set the pad diameter for BGA components in KiCAD?
Trace to BGA Pad Spacing: What is the process for specifying the spacing between traces and BGA pads?
Via Copper to BGA Pad Spacing: Where and how can I input the spacing between the copper of vias and the BGA pads in KiCAD?
I have come across this thread Design rules for JLCPCB on the forum, but it doesn’t seem to address these specific BGA parameters.
BGA Pad Diameter is just a properity of the BGA footprint itself. You can (easily) modify an existing footprint, or use the BGA wizard to make a footprint with custom settings.
For the others, I would start with setting up the normal design rules. If the design rules work for the BGA, then they should also work for the rest of the PCB. But if you want to use coarser rules for the rest of the PCB, then you can create custom design rules for it in KiCad, but this does need some studying. I have collected a few examples of custom rules in:
Design constraints rules should not be part of the library. For example, I have a separate repository for libraries and for projects. I can easily have a project that I will produce at another manufacturer with different typological limits, redesigning the library for every project is not a good solution.
Custom Rules have a Fabrication_Property property. In libraries, this property is set to none for all pads. Is there a way to tag all pads and set this property in bulk?
first remark: it’s always good to write which kicad version you use
Is there a way to tag all pads and set this property in bulk?
depends on kicad version (see remark above):
v6/v7/v7.99:
set the property for the first pad
then open the context-menu (RMB-click) and explore the following functions:
“copy Pad roperties to default”, followed by “Paste default properties to selected”
or “Push Pad properties to other pads”
v7.99/v8: enable the properties panel in the footprint editor, and edit the “fabrication Property” in that panel (works for selected pads)
redesigning the library for every project is not a good solution
If different projects have different requirements regarding the footprints (and pads are a subset of a footprint): yes, you will need different footprints. The purpose of a library is to have some fixed, tested parts (symbols/footprints) which will always behave the same. Making a library-item depending on some external constraint defeats the purpose of a library (my opinion).
DRC-constraints (the basic constraints as well as the custom DRC rules) can be used for:
running the DRC-checks
influence the automatic zone filling
partly influence the interactive router, so some DRC-constraints are already respected during the routing
but DRC-constraints are not supposed to directly modify footprint pads/shapes/whatever
maybe there is the option to write a python script which modifies a pcb-footprint based on the DRC-constraints
If you need a BGA-footprint with multiple different pad-diameters (for different pcb-manufacturers) you could:
work with the largest value from your manufacturers
design multiple footprints in the library (this is the most common concept, compare for instance library capacitor_smd, footprint C0201 ↔ C0201_handsolder)
not recommended from me: modify the footprint later in the board (doubleclick footprint–>Edit Footprint…) and change the pad diameters manually (see bulk-editing pad parameters above)
You can’t design a footprint without determining some kind of size for the pads. Some EDA suites have different sets of libraries depending on the “class” of a design. Libraries for high density boards have small pads so stuff can be packed more closely together, while libraries with larger pads make the PCB manufacturing easier to control and improve reliability.\
I do not know how common this is these days. I am guessing that the quality of (professional) SMT PnP machines has improved to a point that it does not matter as much as it used to (30 years ago). For things like BGA packages, there is also not much difference between the minimum pad size required for soldering, and the maximum pad that would fit.
A lot of KiCad’s footprint libraries are also generated from scripts. Those scripts are on gitlab, but are not part of a regular KiCad install. If you want to modify a lot of footprints, then cloning and modifying those scripts may be a good path to pursue.
At least at this point I have created a python script to add the fabrication Property = pad_prop_bga parameter
import re
import sys
# Function to modify (SMD) pads in the footprint file
def modify_pads(file_path, property_name, property_value=None):
# Regex pattern to match pad lines with (size ...), the second group captures everything after (size ...)
# pad_line_regex = re.compile(r'(\(pad\s+".+"\s+smd\s+circle\s+\(at\s+[\d.-]+\s+[\d.-]+\)\s+\(size\s+[\d.-]+\s+[\d.-]+\))(.*)')
pad_line_regex = re.compile(r'(\(pad\s+".+"\s+smd\s+circle\s+\(at\s+[\d.-]+\s+[\d.-]+.*\)\s+\(size\s+[\d.-]+\s+[\d.-]+\))(.*)')
# Regex pattern to check if the property already exists in a line
property_check_regex = re.compile(rf'\(property\s+{property_name}\s*(\"[^\"]*\")?\)')
# Read the content of the original footprint file
with open(file_path, 'r') as file:
content = file.readlines()
diff_count = 0
# Modify the content
modified_content = []
for line in content:
match = pad_line_regex.search(line)
if match:
# Check if the property already exists in the line
if property_check_regex.search(line):
modified_content.append(line)
continue
# Increment the count of differences
diff_count += 1
# Insert the property between the size and layers parts
# The beginning part of the pad line up to (size ...)
start = match.group(1)
# Everything after (size ...)
end = match.group(2)
property_insert = f' (property {property_name}' + (f' "{property_value}"' if property_value else '') + ')'
modified_line = start + property_insert + end + '\n'
modified_content.append(modified_line)
else:
modified_content.append(line)
# Write the modified content back to the file
with open(file_path, 'w') as file:
file.writelines(modified_content)
print(f"Modified {diff_count} pads in {file_path} with the property '{property_name}'" + (f" set to '{property_value}'" if property_value else " without a value") + ".")
def main():
if len(sys.argv) < 3:
print("Usage: python modify_pads.py <file_path> <property_name> [property_value]")
sys.exit(1)
# Arguments from command line
file_path = sys.argv[1]
property_name = sys.argv[2]
property_value = sys.argv[3] if len(sys.argv) > 3 else None
# Call the modify function
modify_pads(file_path, property_name, property_value)
if __name__ == "__main__":
main()
In the case of BGA Pad Diameter, I would be satisfied with the DRC rule that says whether the given footprint meets the board constrains or not.
In the case of Trace to BGA Pad Spacing, I want it to be part of the specific board constrains. So that the interactive router is guided by this and signaled in the event of a violation.
In the case of Via Copper to BGA Pad Spacing, I want essentially the same behavior as in the case of Trace to BGA Pad Spacing.
In the case of BGA Pad Diameter, I would be satisfied with the DRC rule that says whether the given footprint meets the board constrains or not
This could be implemented in the future with the custom rules system. Currently there is no constraint for pad-size implemented, so no rule to limit the pad-size can be written.
In the case of Trace to BGA Pad Spacing …
I think you mean track ↔ pad spacing?
This can be done with the custom rules system already. Look into the manual, section “Advanced topics–>Custom design rules” : PCB Editor | 7.0 | English | Documentation | KiCad
Someone has a example written especifically for your request:
4- and 6-Layer PCBs
Symbol Description Minimum (mm) Comments
H Via drill diameter 0.2
P Via copper diameter 0.3
B BGA pad diameter 0.25
D Drill to BGA pad spacing 0.2 Solder mask may expand over via if subceeded
S Trace to trace spacing 0.09
C Trace to BGA pad spacing 0.127 BGA pad cut back if subceeded
G Via copper to BGA pad spacing 0.127 BGA pad and via both cut back if subceeded
I think most of these values can be checked with drc custom rules.
note that for a first attempt I would recommend to merge S+C+G and take to greatest value. It’s not necessary to blindly follow the given values.
exceptions:
check for B (minimum BGA pad diameter): I think is not possible with current constraints
check for D (via hole to same-net pad): maybe possible with constraint “physical_hole_clearance”, but I’m not sure
If you write to write some custom rules look in the mentioned thread (by paul) and in the pcbnew-documentation. Both places show some examples.
If you succesful write some rules you could attach tem in this thread. Working examples are always appreciated.
