One of the features I have been looking forward to the most in KiCad 6.0 is the ability to specify design rules that apply only under certain circumstances or between certain net classes.
My simplified use case is half bridge circuit consisting of 2 HV rails, HV+ and HV-, a phase output that could be at HV+, HV- or floating potential depending on the MOSFET states. The low voltage control system is totally isolated from the HV system via an isolation barrier within the gate driver ICs and the isolated power supplies. See the circuit in the diagram.
What I was hoping to do was come up with a set of design rules that would enable me to route this circuit so that there is minimal clearance between traces at close potentials but full clearance between different HV and LV net classes.
My initial approach has been to define 4 main net classes: HV+, HV-, HV phase and LV where each net class contains all the nets at a similar potential as per the diagram.
(version 1)
(rule "LoW cLeArAnce BeTWeen neTS of THe SAme HV potential"
(constraint clearance (min 0.2mm))
(condition " A.NetClass == B.NetClass && A.NetClass == 'HV*' " ))
(rule "HIgH cLeArAnce BeTWeen neTS of dIfferenT HV potentials"
(constraint clearance (min 5.0mm))
(condition " A.NetClass != B.NetClass && A.NetClass == 'HV*' && A.NetClass == 'HV*' " ))
(rule "HIgH cLeArAnce BeTWeen LV And HV neTS"
(constraint clearance (min 5.0mm))
(condition " A.NetClass == 'HV*' && B.NetClass != 'HV*'" ))
(rule "Reduced cLeArAnce for HV PoTenTIALS cLoSe To comPonenTS"
(constraint clearance (min 1mm))
(condition " A.insideCourtyard('*') && A.NetClass == 'HV*' "))
(Note the semi random changing of rule name cases is seemingly unavoidable in the editor at least on Mac, which I presume is a bug)
These rules have sort of worked but I need to be able to reduce the clearance close to certain components, most notably the MOSFETs as they are designed with a lower clearance than I want to use elsewhere. My final design rule was an attempt to solve this but it does not appear to have worked. as I cannot route the source pins of the MOSFET even though they are more than 1 mm from the drain pins.
Am I approaching this the right way? Corrections, suggestions and comments welcomed. I know I am doing something wrong!
One thing I am not certain of is how the design rules interact with each other. My guess would be they are effectively ORed together and the most lenient set of constraints is followed, or is this wrong and they are applied sequentially?