KiCad 6.0 custom design rules for HV clearances

One of the features I have been looking forward to the most in KiCad 6.0 is the ability to specify design rules that apply only under certain circumstances or between certain net classes.

My simplified use case is half bridge circuit consisting of 2 HV rails, HV+ and HV-, a phase output that could be at HV+, HV- or floating potential depending on the MOSFET states. The low voltage control system is totally isolated from the HV system via an isolation barrier within the gate driver ICs and the isolated power supplies. See the circuit in the diagram.

What I was hoping to do was come up with a set of design rules that would enable me to route this circuit so that there is minimal clearance between traces at close potentials but full clearance between different HV and LV net classes.

My initial approach has been to define 4 main net classes: HV+, HV-, HV phase and LV where each net class contains all the nets at a similar potential as per the diagram.

(version 1)

(rule "LoW cLeArAnce BeTWeen neTS of THe SAme HV potential"
	(constraint clearance (min 0.2mm))
	(condition " A.NetClass == B.NetClass && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen neTS of dIfferenT HV potentials"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass != B.NetClass && A.NetClass == 'HV*'  && A.NetClass == 'HV*' " ))

(rule "HIgH cLeArAnce BeTWeen LV And HV neTS"
	(constraint clearance (min 5.0mm))
	(condition " A.NetClass == 'HV*' && B.NetClass != 'HV*'" ))

(rule "Reduced cLeArAnce for HV PoTenTIALS cLoSe To comPonenTS"
	(constraint clearance (min 1mm))
	(condition " A.insideCourtyard('*') && A.NetClass == 'HV*' "))

(Note the semi random changing of rule name cases is seemingly unavoidable in the editor at least on Mac, which I presume is a bug)

These rules have sort of worked but I need to be able to reduce the clearance close to certain components, most notably the MOSFETs as they are designed with a lower clearance than I want to use elsewhere. My final design rule was an attempt to solve this but it does not appear to have worked. as I cannot route the source pins of the MOSFET even though they are more than 1 mm from the drain pins.

Am I approaching this the right way? Corrections, suggestions and comments welcomed. I know I am doing something wrong!

One thing I am not certain of is how the design rules interact with each other. My guess would be they are effectively ORed together and the most lenient set of constraints is followed, or is this wrong and they are applied sequentially?

I also do power, but I have not attempted to dig into design rules to the extent that you are. So far as I know, design rules WRT spacing do not seem to allow for small voltage differentials when they are all at some high voltage (relative to ground for example). So you could have a current sense resistor connected in series with a 500VDC rail, but the maximum voltage between the ends of that resistor might be 100 mV. Or maybe there is an MSOP IC with all of its pins at voltages in the range of +490 to +500 VDC and the pin centers are 0.5 mm. That situation is a bit closer to your half bridge. I would be interested in learning of any solutions to this. I do not use design rules much.

The capitalization out of Apple seems wacko; for some reason it reminds me of a ransom note assembled from newspaper clippings.

What you are hitting looks like the issue I was hitting and I believe the long term solution (v7?) is such that multiple nets can be associated with different net classes so these rules start being manageable.
Having a minimum of 10 different “zones” for a 2level converter (I havn’t even attempted a 3level yet…) start causing issues if you want certain tracking rules for the gatedrive section as well as the switch section.
I looked at modifying an inverter I had and I settled on a few additional zones

  1. LV
  2. HV+
  3. HV-
  4. HV_Ph
  5. GD_Upper
  6. GD_Lower

GD_Upper → HV_Ph is small distance
GD_Lower → HV- is small distance
the other combinations are larger distances

A 1mm Source-Drain? that can only be for a 100-200V MOSFET

So far as I know, design rules WRT spacing do not seem to allow for small voltage differentials when they are all at some high voltage (relative to ground for example).

That aspect of the design rules now works and the rules I posted achieve just that. Feel free to try them out!

I am not too worried about the number of net classes as it is easy enough to keep. on top of them for now but I agree a v7 solution that makes KiCad deal with net ties etc. properly would probably make this much easier.

A 1mm Source-Drain? that can only be for a 100-200V MOSFET

The 1mm spacing is mostly a placeholder for whatever the spacing actually is within the packages.

Is the approach I am taking regarding courtyards to reduce clearance valid? I am not sure I have the syntax or logic quite right.