Moats / Local ground planes: design rule vs. geometric construction

Layout
1

What’s the best way to make polyline cuts in filled zones?

The problem to be solved is the implementation of local ground planes that prevent ground bounce, EMI or ESD transients from perturbing the crystal oscillator of a chip:

image
image911×446 20.5 KB

(source: https://ww1.microchip.com/downloads/en/Appnotes/Atmel-8128-Best-Practices-for-the-PCB-Layout-of-Oscillators_ApplicationNote_AVR186.pdf)

First idea: describe the slot as clearance from a selection of lines in a User layer:

(rule zone_cuts
(layer F.Cu)
(condition "A.Type == 'Zone' && B.existsOnLayer('User.1')")
(constraint physical_clearance (min 0.5mm))
)

… which does not work. I can’t remember whether one could explicitly add layers not part of the design rules processing, or whether graphic items are generally excluded, but this approach does seem to be a dead end here, along with being able to change the width of the feature afterwards.

Instead, it seems one way to accomplish the task is:

  • selecting and changing the width of the line one segment at a time (changing the line width of a selection is not implemented?) or via Edit Text and Graphics Properties to change the line widths of all lines at once
  • optional: create group
  • groups that only contain lines cannot be converted, so enter group, select all
  • right-click Convert > Convert to Rule Area with Create Bounding hull and unticked Delete Source Objects.., sole selection of Keep out copper fill

The result is a line hull-shaped rule area that has to be deleted and re-generated from the lines in the group as needed.

image
image806×847 73 KB

I hope it’s clear why my first idea was to go looking for a design rules - based solution. Am I missing something here?

ps. there is a collection of design rule examples, but maybe we also need a list of examples that cannot be solved with design rules.

2

For me it looks like problem of analog/digital grounds connected in one point. If you use separate Crystal_GND net for this local ground and net-tie to the whole PCB GND then cuts between ground will be done automatically while filling zones (Crystal_GND zone should have higher priority).
But I am writing based on what I have read here at forum - I never used net-tie.

3

Please note the question is about making line-shaped cuts in zones.
Similar to the current density in L-cut trimmed resistors, it is sometimes sufficient to make 1-2 interruptions to isolate ground bounce, without creating a high impedance junction that may also be too narrow, or unable to conduct heat well, as it would be useful e.g. when segregating a DCDC converter.

Note how in the “shadow” of the L-shaped cut, the current density drops to zero when a current is forced in x direction.

image
image1204×429 67.5 KB

4

what about placing an L shaped rule area for keep-out for zones ?
you can put a cut in the zone this way.
they can be placed on the PCB, or they can be part of footprints.

5

From this answer:

I assume you did not fully understand Piotr’s response. The idea is to use a nettie to create a separate net, and create a zone with that net name under the crystal. The net tie then connects it to the GND plane. Then set this zone to a higher priority then the normal GND net and KiCad will draw it first. Then the normal GND zone just overlaps with this new net, and KiCad will automatically calculate the zone boundaries depending on the clearance rules.

Another option is to draw no GND zone under the crystal at all. This reduces parasitic capacitance on the nets for the crystal. Apparently this is method is also quite popular, but I don’t know which is “best”.

6

Pads under the crystal are usually hundreds of femtofarads… (but subject to variation).
Certainly, noise can be injected into the crystal circuit by noisy grounds, so a ground moat / cut is a good way to avoid that. If its just a microprocessor clock, I would say ’ why bother’ because the jitter inside the device will be ++ anything into the crystal. but it might be some GHz retiming clock…also you have to be a bit careful with low C watch crystals.

7

Quantifying the impacts briefly remains a challenge, indeed. Thanks for pointing out the term “moat”, been missing that.

As for the circuit section: it’s a 4-layer PCB with power nets running underneath the oscillator section, and there are LDOs on the front side (above the crystal as shown in the image above), so I thought it prudent to at least prevent any currents from flowing past the crystal. I had had the copper removed underneath the crystal and capacitor courtyards, but then decided in favor of Faraday shielding.
My thought is that the additional capacitive loading can be absorbed into the discrete capacitor values, or the additional pulling can for the most part be ignored.
The oscillator section belongs to a clock generator IC which provides the main clocks to two PLLs.

image
(source)

8

Whether the power traces underneath cause trouble would be very solution specific. I wouldnt care about a power or ground plane- the current density is likely very low.
Moats are pretty common.
In RF directional couplers I build in radios, I might be looking for coupled signals 1/10,000th of the mainline (5000W) signal, so I need to take care that mainline ground returns do not have the opportunity to flow through the coupler region.

1 Like
9

Before this thread closes - I consider opening it a failure. I presented two approaches I tested, including the second one which is the actual solution I chose, yet for some reason some have found it necessary to explain why I must want another solution that is inferior and not what this thread was about initially:

  • lines in user layers could not be made to affect zone fill
  • hulls can’t be created from a group of lines, only from a selection of lines, which means there is missing support for the expansion of groups
  • changing the width means throwing away the resulting rule area, updating line widths (one by one, because multi-edit is not implemented for lines), and finally generating a new hull

So the correct answer is: most of the features needed to do it better than described above DON’T WORK, and that’s why there is currently no more elegant or effective way to do it.

10

To give you some additional ideas (and not discuss why you want this):

  • draw lines on the margin layer. Affects all layers and all copper items, so will work only at some situations. Note that the global constraint for “copper to edge clearance” must be set > 0
  • draw lines on copper layer. They get a “no net” attribute and will be isolated from all copper fills. You have to draw these lines on every copper layer you need the copper fill barrier. You will end up with “useless” copper lines, which might waste space, so this is also not for every situation

Also you could try the just released v8. It makes your current solution nr.2) a little bit easier:

  • convert lines–>rule aree still doesn’t works with lines embeedded in groups
  • but the command “select/expand connection” now works also with graphic lines, so the selection is easier
1 Like