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Layout questions
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2
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301
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January 14, 2025
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Keyestudio Libs
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3
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356
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April 13, 2025
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Slotted pads along board edge for screw terminal
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8
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555
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April 13, 2025
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Esp32-s3c devkit footprint and symbol woes
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14
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2980
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April 12, 2025
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VRML has an extra outer layer
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2
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377
|
April 11, 2025
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ATX, micro, dtx, itx motherboard and slots layout script
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1
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464
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April 11, 2025
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Question for unlocking using V 8.0
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3
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290
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April 11, 2025
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Min groove width
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3
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263
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April 10, 2025
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PCB Design - RF SMA connector with Baluns
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2
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809
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April 10, 2025
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Pads connect to planes but via won't
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6
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294
|
April 10, 2025
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Design rules for skew/length tuning (9.0 rc1)
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8
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622
|
April 10, 2025
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PCB auto-finish track
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15
|
632
|
April 10, 2025
|
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Trouble Tracing USB Signal with Defined Net Class in KiCad
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4
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301
|
April 10, 2025
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Unable to connect track to pad Or Pad unrecognized
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31
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850
|
January 9, 2025
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Castellated holes
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2
|
480
|
April 9, 2025
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Designing footprints with pcbnew Python scripting - how to save to library?
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3
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384
|
April 9, 2025
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Easy access to interactive router mode
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13
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459
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April 9, 2025
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Part ss having the value from schematic
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16
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249
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April 9, 2025
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Text variable
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18
|
675
|
April 9, 2025
|
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Silkscreen items shown in 3D view but not in Gerbers
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35
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725
|
April 9, 2025
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Uploaded files
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2
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274
|
January 9, 2025
|
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How to drag a selection of a layout without disconnecting tracks?
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2
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278
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April 8, 2025
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Silkscreen missing
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2
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380
|
January 8, 2025
|
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Web Viewing of KiCad files - 2
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10
|
950
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April 8, 2025
|
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Capacitor THT Radial Footprint Heights
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8
|
1347
|
April 8, 2025
|
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DRC Outline overylay while routing a track - GPU or kicad bug?
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3
|
272
|
April 7, 2025
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Custom DRC for Overlapping Footprints Silkscreen Elements
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9
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396
|
April 7, 2025
|
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Web Viewing of KiCAD Files
|
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28
|
20722
|
January 7, 2025
|
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Error annular width, wrong annual
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5
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321
|
April 7, 2025
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Environment Variables in Drawing Sheet file path crashes Python plugin invocation from script
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1
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190
|
April 7, 2025
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