Heat sink and thermal pad

I need to design that kind of pattern. The red pattern is component side,
the green pattern is the opposite side. Basically the layout of the component
is only defined on the component side, but I would like to have an exposed
pad also on the opposite side. How can I do that?

I thought I could define a copper fill area, but in this case, the area would
be covered with the board insulation layer, so it wouldn’t work.
NB: It’s a 5x5 laser driver for 3A CW operation, so it has to dissipate a lot
of power from the thermal pad. The only solution is to have a radiator on the
opposite side, and that’s why I wanted a thermal pad on the solder side.

How can this be done? Maybe by defining a thermal pad symbol and component?
Does anybody have an experience for that kind of high power component?

Thanks for any hint.



If you are going to put a heat sync on that pad then why not go that route? I have no practical experience to offer but would a board cutout be better for direct thermal contact or is the sync to large?

In critical cases like this it is always best to start out with the component manufacturer’s design recommendations. Anything goes from there. After that it’s anyones guess.

Putting a heatsink component on the opposite side sounds like a good idea to produce the exposed pad on the opposite side. But I do not like the cutout as it may present mechanical problems, such as mechanical support of the IC and of the heatsink.

One more comment; I have been favorably impressed at the ability of pcb copper to accomplish heatsinking. So if you have a 4 layer board (less likely with a 2 layer board) and can put a large copper zone there it will often work nicely.

Perhaps I do not understand the question, but here’s the approach I would try:

  1. Open KiCAD’s Footprint Editor. Start with a basic QFN-28 footprint, such as you find in the KiCAD library.

  2. Define an SMD pad on the BACK SIDE, with a suitable size. Give it the SAME PAD NUMBER as the top-side thermal pad. It needs to be defined on the back-side mask layer (so it will be exposed), but you will probably EXCLUDE it from the back-side paste layer. You may also want to define a “SOLID” connection to Copper Zones.

  1. Define a thru-hole pads to serve as “thermal via”. It must also have the same pad number as the top-side thermal pad.

As a practical matter, the amount of annular ring on this pad is irrelevant since the pads will be merged into the larger thermal pad. However, your board fabricator’s DFM software may squawk if the annular ring doesn’t met the requirements for annular rings on all other pads.

  1. Replicate the pad defined in step 3. (above) as many times as necessary.

You may define each pad individually, or “Duplicate”-and-position (keyboard shortcut ctrl-D ) each pad, or use the “Create Array” feature (ctrl-N).

  1. Save this footprint with a NEW NAME, in your personal library, so it won’t get over-written the next time you update KiCAD!

  2. If you will connect the thermal pad to an electrical net in your circuit - such as a ground plane, or power bus - then the component’s symbol in your schematic must include a pin for the thermal pad, and your schematic must show the electrical connection to that pin.

The hole in the thermal vias deserves some attention.

  • It must be large enough that your board fabricator can manufacture it. 0.5mm (20 mils) is probably a safe bet for any manufacturer using equipment less than 20 years old. Many fabricators can do 0.35mm (15 mils) on a “standard” order, and you may find a few who will accept jobs with 0.3mm (12 mils) or even 0-25mm (10 mils) holes.

  • It is commonly believed that heat transfer from the top side to the bottom side is improved if the holes are filled with solder during manufacturing. I don’t know if there is credible evidence to support this idea.

  • Your manufacturing engineer may curse you for even putting the holes there. They certainly suck up solder paste from the top-side thermal pad. That paste may fall through the hole, and make a mess inside the reflow machinery. Providing your manufacturing engineer with a serving of his favorite malt beverage may, or may not, appease him.

  • Your board manufacturer may be able to supply boards with the holes already plugged with solder, epoxy, or other material. This is almost certainly an extra-cost option.

The general topic of components with thermal pads has been discussed several times on this Forum. Some of the threads are:
How to add via holes on a thermal pad of QFN footprint?
Pad Holes Under SMT for Heat Sinking and other questions
A help with QFN footprint with thermal vias and solder paste
Creating Exposed (Thermal) Pads
Thermal Pad, Solid vias, Thermal Relief, (complete noob)
Assign a pin to a thermal pad?
Thermal pads, stitching vias and DRC errors


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@dchisholm you might need to update your footprint lib :wink: The footprint you show is made in a style we really no longer use.

@roboya see Tutorial: How to make a footprint in KiCad 5.1.x (From scratch)? Section Example footprint QFN-64 with exposed pad (Calculate land pattern from part dimensions) for details about how we now do it. Also we have a script https://github.com/pointhi/kicad-footprint-generator/tree/master/scripts/Packages/Package_NoLead__DFN_QFN_LGA_SON Usage is very similar to the gullwing script that has its documentation here https://github.com/pointhi/kicad-footprint-generator/blob/master/scripts/Packages/Package_Gullwing__QFP_SOIC_SO/Readme.md

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Thanks for your reply. That’s exactly what I was trying to do, but it didn’t work the same on my foot print editor. I have tried to make another pin 29 which is larger, and set it to the opposite side. That’s where it started to go wrong. It used to be as follows but that’s simply because Id didn’t check B.mask.

Now it works!

Thanks a lot!


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I am quite certain you are correct. I think that footprint is from an old version 4.?.? library, that is on the old laptop I’m using at the moment. I hoped it was adequate to illustrate the process I was explaining. (Did you notice that I didn’t attach a copy of the resulting footprint file to my post? That wasn’t an oversight - I don’t want to be known for proliferating obsolete files.)


Yes it is from version 4. Can be found out because its name is in the old style. The word pitch is no longer written in full, and we now include the size of the exposed pad as a parameter as there are a lot of different pad sizes for the same body size.

We also no longer use multiple copper pads to define the center pad as this makes it a lot more likely that the resulting sizes is not what one expects (because it is easy to make a mistake this way) we split the paste layer by introducing paste only pads as required.


In critical cases like this it is always best to start out with the component manufacturer’s design recommendations. Anything goes from there. After that it’s anyones guess.

Indeed. And he recommends to have a heatsink on the opposite side. My question was related to how to do it. The PCB itself, even 4 layers is not enough. For instance with a close infrared laser, you get a voltage of 2V across the diode. But most of the power will be dissipated in the chip, and cooling so much power through a 3 x 3 mm thermal pad is not trivial.


You give a lot of trust in the intern that copies the information from a similar product. Plus most documentation uses outdated industry standards.

If it is really critical then one might be better off to start from scratch with the package dimensions and a footprint generator that follows a modern industry standard.

One would also need to set your own manufacturing parameters. The industry standard defines one parameter for your board manufacturers tolerances and one for your assembly tolerances. Both parameters that neither the part manufacturer knows, nor we librarians. (That is why a generator is the way to go here.)

Vias in the pad are a bit of a tradeoff. Place too many and you get the potential for voiding. Here the manufacturers suggestion can be used as a starting point, but if it is really critical then modelling the heat flow in a simulation tool might be in order. (The guys writing the documentation mostly go by gut feeling and err on the side of too many and or too large vias. Voiding is your problem to deal with not theirs)

You might need to talk to your manufacturer if filling them with metal is an option. This increases the thermal conductivity and reduces the risk of voiding. Otherwise, use the smallest drill size possible to reduce the amount of solder you loose through each via and increase paste coverage ratio (TI suggests <0.3mm final hole size).

TI suggests you should end up with at least 50% contact area after soldering (for high thermal load applications). So in critical situations an after production check via x-ray machine might be in order. Maybe make a few test boards beforehand and tune your production.

I have had to deal with a similar problem in the past, in our case getting >20W out of an SMD0.5 package and through a 2mm 10 layer PCB to a heatsink. This was in Allegro rather than KiCAD but the approach still works at a cost, this is an application where cost is very secondary to long term reliability.

Thermal vias not part of the footprint but added after, 0.2mm hole at 1.25mm pitch, vias 100% fill and plate both sides (IPC 4761 type 7)

Make as big a shape as you can get away with on every layer underneath your device and connect together with thermal vias over as big an area as you can. If you can, use a heavy copper layer on L2 and Ln-1, we use 4oz but not many fabs can handle that, 2oz will still help. Hopefully your device thermal pad connects to GND which makes life easier and if you can put your device near a plated through fixing that connects to your chassis you get an easy extra thermal path out of the board

Hope that helps

Hello Stair!
Thanks for your reply. It makes sense. I cannot use more than 2 layers, and I hope the 25 vias I have punched will help sinking a lot of heat. I will use a PC CPU cooling with a turbine, so I guess it will help. In a first development, I will use standard circuit that you can get developed for 5 euros. Therefore, no way to get more than 35 microns thickness. I will have to make sure the vias are filled… I have used 0.3 mm drills otherwise the cost climbs. But in fact, now I have made the library part, and I guess I’m on the right way for a fair cooling.
A laser in CW doesn’t need high voltage because the edges are not really important, so I think the power dissipation can be moderate. And in pulse mode, the ratio is usually small so the voltage can be increased without too much power dissipation.

Thanks for the hints, anyway.


Latest news: I’ll go for an aluminium PCB. Single face, so I will have to remove the vias, but it’s not that expensive and it will be unbeatable in terms of power dissipation. Sorry for all this mess but I’m sure it will be useful in the future, for me or somebody else.

Since we talk about significant heat transfer, keep in mind that Al has a substantial thermal expansion coefficient!

Beware of mirco cracking the chip.

The solder plasticity may not be sufficient to compensate.


Hello Jos!

Very useful input. I will check with the chip maker to know what he thinks about this issue.
Not sure that the displacement would be big enough to crack the chip, and not sure about the
dilatation of the chip material but it’s a good idea to consider it.


This information could be of assistance as well.

Hello Jos!
Thanks for the document. Many useful hints here.
About aluminium PCBs: I know that this question is not really Kicad related, so to the moderators, pleas cut this question if you thinks it’s not appropriate.
What I designed above is for regular epoxy PCB, and vias are needed to draw as much heat as possible. I have checked about aluminium PCBs, and some makers can produce 2 sided PCBs. But in this case, I suppose I don’t need vias, right? It would more likely harm the heat trasfrer rather than help it.
Thanks for any hint.

That is correct.
Vias in this case represent small cavities most likely filled with air which happens to be an insulator. Therefore small heat ‘bubbles’ form around each via which in turn can hamper heat transfer.

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