Thermal pads, stitching vias and DRC errors

I’m wrapping up my second board in KiCad (moving from Eagle). Things look good, generally, but I’m having problems with vias connecting thermal pads underneath the chips. First, I had no idea how to place them. I worked around that by starting a track, then pressing V to get a via, then immediately ending the track. Feels hacky and messy, but seems to work for most of my stitching vias.

I do not understand, however, the DRC errors that I get (please see picture). And I seem to get them only sometimes, not for every chip with thermal pads.

Any suggestions?

try to have a look here


Switching to classical mode would show the clearances, whicht might help.

Did you start the ‘tracks’ to those thermal vias from the ‘track attaching point’ at those thermal pads underneath the chips?

People usually use PTH footprints for these kind of things as vias tend to be fickle about their miss-treatment.

Problem solved. It turns out that those were not my footprints, but ones found in KiCad. Those have the thermal pad as a pin (17 in this case), which does not correspond to anything on the schematic. For some reason the DRC does not warn about this. After I placed my vias to ground, DRC did complain, but I could not understand the message.

To fix the problem, I had to go and edit each of the four pads, setting the net to GND for each of them, and then recreate the vias.

Thanks for the help!