A help with QFN footprint with thermal vias and solder paste

Hello all,

I’m defining a footprint for a kind of QFN that has thermal vias in its center.

I follow the suggestions I read here in the forum and added pads using same number. (see picture 1).

The vias in the footprint seems to be ok, when I’m not selecting the F.Paste (see picture 2).

But if I do select F.Past, then I can’t see the roles anymore, even with a solder paste cleareance definided in each role pad (see picture 3).

There are any way to workaround and have the roles drawn even with a solder paste in the center ?

thanks for any tip.


you can use the script generator in kicad:

Normally you have to use pads and not vias for thermal stitching

Hi Maui, good to know about this awesome footprint wizard ! :slight_smile:

I played a bit with it right now… but even in the ones generated by it I can’t have clearance around the roles in the F.Paste.

is this not possible currently, perhaps ?

The pad looks large enough that you should break up the solder paste anyway. I would remove the solder paste layer from the main pad (but leave the soldermask aperture) then I would add 4 rectangular pads within the main pad (all with the same number ‘49’) with an active paste mask. You still won’t quite get the visual result you want - your 4 innermost vias will still be completely covered by paste and the 8 outer ones will be half covered. This is all a natural consequence of your design - there is no reason to expect the vias to be exposed when you have instructed the software to put paste over them.

are you looking for a Paste mask over vias?
Is that any doc that has suggested that?
if you look at TI manufacturer QFN layout guidelines
you will see they suggest solid vias

and stencil without a keep-out Paste zone

NXP suggests eventually to tent vias, but this is controversy among manufacturers

I was looking for a way to create a footprint based on the SMD Windows suggested by this article.

something like this board: http://www.pcdandf.com/pcdesign/images/stories/ArticleImages/1603/ibm16.jpg

nice article…
anyway the ways to create thermal vias have pros and cons…
one solution could be like the following picture from the same article

but in my prods I used the TI suggested one, with drills of the suggested dimension, as per specific chip doc…

Hi maui,

I’m new to QFN packages, but an old friend of mine (that recommended the article) is using them a couple of years and have warned me about possible issues.

I also used to follow the footprints provided in datasheets, but in case of QFN, following them can cause some issues. For example, following the TI datasheet’s recommend stencil will inevitably left some pad vias exposed to solder paste.

So, depending on the amount of solder paste that were applied two problems can arise. If the solder paste layer were too thin then your board can end with voiding as showed in the Rx below:

In the other hand, if excessive solder paste where used, then you can have problems with solder wicking variability:

Or can be a bit worse and end up with solder protrusions on the pad vias as stated in the image bellow:

I played a little bit and created a footprint using smd 10 pads with F.Past layer only.
I will try to use it in a new prototype soon after receive the board manufacturing ok first, of course :slight_smile:

for that reason I used what TI suggested…

  1. the amount of Paste is reduced because of smaller Paste pads footprint
  2. the risk of solder sicking is reduced by small drill size
    I didn’t have any issue in my prods followings these suggestions…

so what your friend is suggesting as a solution (not just the warning)?

The company that he is working is using the SMD Window design suggested in the article.

something like what you did and as in the article?
and is there also solder mask on main pad?

Are you using a footprint with 25 via holes (0,3mm) and a stencil with 9 squares of 1,45 x 1,45mm ?

Yep, that is what this research is recommending…

humm I didn’t use any solder mask over the main EPad… (I mean the main EPad was free of mask, copper in view)
In your chip is there a big pad connected to vias? I don’t see it on your first picture

Seem that you are using the common current practice “option 1” below:

[quote=“maui, post:17, topic:5293, full:true”]In your chip is there a big pad connected to vias? I don’t see it on your first picture
That is the chip I’m about to use:

Let us know how things go when you do another run. I guess leaving the solder mask within the pad helps prevent migration of the solder (especially down the vias) but shouldn’t otherwise interfere (typical soldermask thickness = 0.012mm). Typical manufacturer recommendations I’d seen suggest that a 30% contact surface is what they aim for.

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Looking at all those pictures… in the end the solution will be to have a raster of BGA like solder pads interleafed (half pitch) with a grid of vias.
No messing around with special pad shapes etc.
Just make the BGA thermal contact pads as big as you need to get 50% contact area and wetting/contact should be no big deal as the gas/air can escape into all directions.

Something like a 2D NaCl crystal cage.
Maybe the pads can even be simple squares, to get more thermal conductive area out of it (45 deg rotated).
Anything more complicated than that is begging for trouble IMHO.

Those X-Rays look like air/gas trapped within the solderpaste and not being able to get out during reflow.

I think that those pictures alone without a good context maybe do not reflects its real purpose, perhaps would be better read the article where they came from. There you will find more complete explanations. :wink:

an other nice doc about it